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CA3290AE bảng dữ liệu(PDF) 4 Page - Intersil Corporation

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Giải thích chi tiết về linh kiện  BiMOS Dual Voltage Comparators with MOSFET Input, Bipolar Output
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CA3290AE bảng dữ liệu(HTML) 4 Page - Intersil Corporation

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4
Circuit Description
The Basic Comparator
Figure 4 shows the basic circuit diagram for one of the two
comparators in the CA3290. It is generically similar to the
industry type “139” comparators, with PMOS transistors
replacing PNP transistors as input stage elements. Transistors
Q1 through Q4 comprise the differential input stage, with Q5
and Q6 serving as a mirror connected active load and
differential-to-single-ended converter. The differential input at
Q1 and Q4 is amplified so as to toggle Q6 in accordance with
the input signal polarity. For example, if +VIN is greater than
-VIN,Q1,Q2, and current mirror transistors Q5 and Q6 will be
turned off; Transistors Q3, Q4, and Q7 will be turned on,
causing Q8 to be turned off. The output is pulled positive
when a load resistor is connected between the output and V+.
In essence, Q1 and Q4 function as source followers to drive
Q2 and Q3, respectively, with zener diodes D1 through D4
providing gate oxide protection against input voltage
transients (e.g., static electricity). The current flow in Q1 and
Q4 is established at approximately 50µA by constant current
sources I1 and I3, respectively. Since Q1 and Q4 are
operated with a constant current load, their gate-to-source
voltage drops will be effectively constant as long as the input
voltages are within the common-mode range.
As a result, the input offset voltage (VGS(Q1) + VBE(Q2) -
VBE(Q3) - VGS(Q4)) will not be degraded when a large
differential DC voltage is applied to the device for extended
periods of time at high temperatures.
Additional voltage gain following the first stage is provided by
transistors Q7 and Q8. The collector of Q8 is open, offering
the user a wide variety of options in applications. An
additional discrete transistor can be added if it becomes
necessary to boost the output sink current capability.
The detailed schematic diagram for one comparator and the
common current source biasing is shown on the front page.
PMOS transistors Q9 through Q12 are the current source
elements identified in Figure 4 as I1 through I4, respectively.
FIGURE 2. NON-INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
FIGURE 3. INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
Test Circuits and Waveforms
INPUT
OVERDRIVE
GND
100mV
OVERDRIVE
20mV
OVERDRIVE
5mV
OVERDRIVE
INPUT
OVERDRIVE
GND
100mV
OVERDRIVE
20mV
OVERDRIVE
5mV
OVERDRIVE
+15V
1K
1K
INPUT
5.1K
OUTPUT
+
-
INPUT
OVERDRIVE
GND
100mV
OVERDRIVE
20mV
OVERDRIVE
5mV
OVERDRIVE
INPUT
OVERDRIVE
GND
100mV
OVERDRIVE
20mV
OVERDRIVE
5mV
OVERDRIVE
+15V
1K
1K
INPUT
5.1K
OUTPUT
+
-
CA3290, CA3290A


Số phần tương tự - CA3290AE

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