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AD6121 bảng dữ liệu(PDF) 2 Page - Analog Devices |
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AD6121 bảng dữ liệu(HTML) 2 Page - Analog Devices |
2 / 16 page –2– REV. B AD6121–SPECIFICATIONS (TA = +25 C, VCC = 3.0 V, LO = 2 IF, REFIN = 1.23 V, LDO Enabled, unless otherwise noted) Note: All power measurements in dBm are referred to 1 k unless ZIN is noted. Specification Conditions Min Typ Max Units TOTAL GAIN Maximum Gain IF Amplifiers and Demodulator Powered Up +47 dB IF Amplifiers Powered Up and Demodulator Powered Down +41.4 dB Minimum Gain IF Amplifier and Demodulator Powered Up –47.5 dB IF AMPLIFIER CDMA and FM Input IF = 85.38 MHz Noise Figure Maximum Gain 5.9 dB Input Third-Order Intercept Maximum Gain –42.8 dBm Input 1 dB Compression Point Maximum Gain –51.6 dBm Gain Flatness IF ±630 kHz, CDMA Mode ±0.25 dB CDMA Input Capacitance Differential 2.8 pF CDMA Input Resistance Differential 850 Ω FM Input Capacitance Differential 2.3 pF FM Input Resistance Differential 670 Ω Output Capacitance Differential 1.35 pF Output Resistance Differential 1.1 k Ω GAIN CONTROL INTERFACE Gain Scaling Using Internal Reference 52.5 dB/V Gain Scaling Accuracy Within a Gain Control Range of 90 dB ±3 dB/V Gain Control Response Time Minimum Gain to Maximum Gain 695 ns Input Resistance at REFIN 10 M Ω Input Resistance at VGAIN 100 k Ω DEMODULATOR LO = 172.76 MHz , –15 dBm Referred to 50 Ω, Baseband Frequency = 1 MHz Differential Input Impedance 1k Ω Differential Input Capacitance at Demodulator Input 2.9 pF Input Third Order Intercept –6.1 dBm Demodulation Gain 5.6 dB I/Q Output Differential Output Voltage 10 k Ω, 2 pF Differential Parallel Load Impedance 700 mV p-p Bandwidth –3 dB 16 MHz Resistance Single-Ended 630 Ω Quadrature Accuracy ±2.5 Degree Amplitude Balance ±0.1 ±0.35 dB LO Input Impedance Differential 1.5 k Ω LO Input Capacitance Differential 4.16 pF CONTROL INTERFACES Logic Threshold High 1.34 V Logic Threshold Low 1.30 V Input Current for Logic High 0.1 µA Mode Control Response Time CDMA/FM Pin High Selects CDMA, Low Selects FM 430 ns Turn-On Response Time PD1 and PD2 Pins Low Select IC ON, High Selects IC OFF 2.8 µs Turn-Off Response Time To 200 µA Supply Current 6.8 µs LOW DROPOUT REGULATOR External PNP Pass Transistor, VCESAT = –0.4 V Max hFE = 100/300 Min/Max Input Range 2.9 4.2 V Nominal Output 2.70 V Voltage Drop 200 mV Reference Output 1.23 V POWER SUPPLY Supply Range Using Internal LDO Supply Input at Pin LDOE 2.9–5.0 V Supply Range Bypassing Internal LDO Supply Input at Pins DVCC, IFVCC, LDOC 2.7–3.6 V Supply Current VGAIN = 1.5 V 10 mA Standby Current 0.78 µA OPERATING TEMPERATURE TMIN to TMAX –40 +85 °C Specifications subject to change without notice. |
Số phần tương tự - AD6121_15 |
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Mô tả tương tự - AD6121_15 |
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