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AD5378 bảng dữ liệu(PDF) 1 Page - Analog Devices

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Giải thích chi tiết về linh kiện  32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC
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AD5378 bảng dữ liệu(HTML) 1 Page - Analog Devices

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32-Channel, 14-Bit, Parallel and
Serial Input, Bipolar Voltage Output DAC
AD5378
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005–2009 Analog Devices, Inc. All rights reserved.
FEATURES
32-channel DAC in 13 mm × 13 mm 108-lead CSPBGA
Guaranteed monotonic to 14 bits
Buffered voltage outputs
Output voltage span of 3.5 V × VREF(+)
Maximum output voltage span of 17.5 V
System calibration function allowing user-programmable
offset and gain
Pseudo differential outputs relative to REFGND
Clear function to user-defined REFGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
DAC increment/decrement mode
Channel grouping and addressing features
Interface options
Parallel interface
DSP/microcontroller-compatible 3-wire serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
SDO daisy-chaining option
Power-on reset
Digital reset (RESET pin and soft reset function)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOAs)
Optical switches
Industrial control systems
FUNCTIONAL BLOCK DIAGRAM
VCC
VDD
VSS
AGND
RESET
POWER-ON
RESET
DGND
LDAC
VBIAS VREF1(+) VREF1(–) REFGND A1
VBIAS
DAC 0–1
DAC
REG
0–1
DAC
REG
2
DAC
REG
5
DAC
REG
6–7
INPUT
REG
0–1
INPUT
REG
2
INPUT
REG
5
INPUT
REG
6–7
DAC 2
DAC 5
DAC 6–7
AD5378
DCEN/WR
SYNC/CS
REG0
REG1
DB13
SCLK/DB12
DIN/DB11
DB0
A7
A0
SER/PAR
DIN
SCLK
SDO
FIFOEN
REFGND B1
REFGND B2
REFGND C1
REFGND C2
REFGND D1
REFGND D2
BUSY
VREF2(+) VREF2(–) REFGND A2
CLR
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
VOUT 7
VOUT 8
VOUT 31
4
14/
14/
14/
14/
14/
14/
14/
14/
14/
14/
14/
14/
14/
14/
m REG0–1
c REG0–1
m REG2
c REG2
m REG7
c REG7
m REG8–9
c REG8–9
14/
14/
14/
14/
14/
14/
14/
Figure 1.
Protected by U.S. Patent No. 5,969,657 and 6,823,416; other patents pending.


Số phần tương tự - AD5378_15

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