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AD5329 bảng dữ liệu(PDF) 3 Page - Analog Devices |
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AD5329 bảng dữ liệu(HTML) 3 Page - Analog Devices |
3 / 4 page Two’s Complement, Dual 12-Bit DAC AD5329 REV PrC 20 DEC 99 – 3 – Information contained in this Preliminary Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 562-7254; FAX 408 562-7154; email; walt.heinzer@analog.com ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless otherwise noted) VDD to GND ........................................................... -0.3,+6V VOUTA, VOUTB, VBZ to GND....................................... 0V, VDD Digital Input Voltages to GND ....................... 0V, VDD+0.3V Operating Temperature Range.......................... 0°C to +70°C Maximum Junction Temperature (TJ MAX)................. +150°C Storage Temperature ................................... -65°C to +150°C Lead Temperature (Soldering, 10 sec) ....................... +300°C Package Power Dissipation....................... (TJMAX - TA) / θJA Thermal Resistance θ JA, µSOIC-10 .....................................................206°C/W AD5329 Two’s Complement Coding Binary Hexadecimal Scale 0111 1111 1111 7 F F +FS 0111 1111 1110 7 F F +FS-1LSB 0000 0000 0001 0 0 1 BZS+1LSB 0000 0000 0000 0 0 0 BZS 1111 1111 1111 F F F BZS-1LSB 1000 0000 0001 8 0 1 -FS+1LSB 1000 0000 0000 8 0 0 -FS TABLE 2: AD5329 PIN Descriptions Pin Name Description 1 VDD Positive power supply, specified for operation at +5V. 2 SDA Serial Data Input, MSB first format 3 NC No Connect 4 VOUTB DAC B Voltage Output (A0 = logic “1”) 5 VOUTA DAC A Voltage Output (A0 = logic “0”) 6 VBZ Virtual Bipolar Zero (Active Output) 7 NC No Connect 8 FSYNC Frame Sync Input, Active Low. When FSYNC returns HIGH data in the serial input register is transferred into the DAC register. 9 SCLK Serial Clock Input, positive edge triggered 10 GND Ground TABLE 1: AD5329 Serial-Data Word Format ADDR DATA B16 B15 B14 B13 B12 B11 <> B4 B3 B2 B1 A0 X SD 0 D11 D10 <> D3 D2 D1 D0 MSB LSB SD: Shutdown is active high B14="1". Both DACs and the DACREF becomes open circuit. SDI AD5329 1 0 1 SCLK 0 1 FSYNC 0 A0 X SD 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 1A. Timing Diagram |
Số phần tương tự - AD5329_15 |
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Mô tả tương tự - AD5329_15 |
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