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74LVC04ABQ bảng dữ liệu(PDF) 3 Page - NXP Semiconductors

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74LVC04A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 17 November 2011
3 of 15
NXP Semiconductors
74LVC04A
Hex inverter
5.2 Pin description
6.
Functional description
[1]
H = HIGH voltage level; L = LOW voltage level
7.
Limiting values
[1]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
The output voltage ratings may be exceeded if the output current ratings are observed.
[3]
For SO14 packages: above 70
C derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60
C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
C derate linearly with 4.5 mW/K.
Table 2.
Pin description
Symbol
Pin
Description
1A, 2A, 3A, 4A, 5A, 6A
1, 3, 5, 9, 11, 13
data input
1Y, 2Y, 3Y, 4Y, 5Y, 6Y
2, 4, 6, 8, 10, 12
data output
GND
7
ground (0 V)
VCC
14
supply voltage
Table 3.
Function table[1]
Input nA
Output nY
LH
HL
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.5
+6.5
V
IIK
input clamping current
VI <0
50
-
mA
VI
input voltage
[1]
0.5
+6.5
V
IOK
output clamping current
VO >VCC or VO <0
-
50
mA
VO
output voltage
[2]
0.5
VCC +0.5
V
IO
output current
VO =0V to VCC
-
50
mA
ICC
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
Tamb = 40 C to +125 C
[3] -
500
mW


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