28F010

With CE

and OE

at a logic low level raising A9

vates the operation Data read from locations 0000H

and 0001H represent the manufacturer’s code and

the device code respectively

The manufacturer- and device-codes can also be

read via the command register for instances where

the 28F010 is erased and reprogrammed in the tar-

get system Following a write of 90H to the com-

mand register a read from address location 0000H

outputs the manufacturer code (89H) A read from

address 0001H outputs the device code (B4H)

Write

Device erasure and programming are accomplished

via the command register when high voltage is ap-

serve as input to the internal state-machine The

state-machine outputs dictate the function of the

device

The command register itself does not occupy an ad-

dressable memory location The register is a latch

used to store the command along with address and

data information needed to execute the command

The command register is written by bringing WE

to

is low Addresses

are latched on the falling edge of WE

while data is

latched on the rising edge of the WE

pulse Stan-

dard microprocessor write timings are used

Refer to AC Write Characteristics and the Erase

Programming

Waveforms

for

specific

timing

parameters

COMMAND DEFINITIONS

tents of the command register default to 00H en-

abling read-only operations

write operations Device operations are selected by

writing specific data patterns into the command reg-

ister

Table 3 defines these 28F010 register

commands

Table 3 Command Definitions

Command

Cycles

Req’d

Bus

First Bus Cycle

Second Bus Cycle

Read Memory

1

Write

X

00H

Read Intelligent Identifier

3

Write

IA

90H

Read

IA

ID

2

Write

X

20H

Write

X

20H

2

Write

EA

A0H

Read

X

EVD

2

Write

X

40H

Write

PA

PD

2

Write

X

C0H

Read

X

PVD

2

Write

X

FFH

Write

X

FFH

NOTES

1 Bus operations are defined in Table 2

Addresses are latched on the falling edge of the WE

pulse

4 Following the Read inteligent ID command two read operations access manufacturer and device codes

5 Figure 6 illustrates the Quick Erase Algorithm

6 Figure 5 illustrates the Quick Pulse Programming Algorithm

7 The second bus cycle must be followed by the desired command register write

8