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N28F001BX-T150 bảng dữ liệu(PDF) 6 Page - Intel Corporation

tên linh kiện N28F001BX-T150
Giải thích chi tiết về linh kiện  1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
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nhà sản xuất  INTEL [Intel Corporation]
Trang chủ  http://www.intel.com
Logo INTEL - Intel Corporation

N28F001BX-T150 bảng dữ liệu(HTML) 6 Page - Intel Corporation

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28F001BX-T28F001BX-B
PRINCIPLES OF OPERATION
The 28F001BX introduces on-chip write automation
to manage write and erase functions The write state
machine allows for 100% TTL-level control inputs
fixed power supplies during erasure and program-
ming minimal processor overhead with RAM-like
write timings and maximum EPROM compatiblity
After initial device powerup or after return from
deep powerdown mode (see Bus Operations) the
28F001BX functions as a read-only memory Manip-
ulation of external memory-control pins yield stan-
dard EPROM read standby output disable or Intelli-
gent Identifier operations Both Status Register and
Intelligent Identifiers can be accessed through the
Command Register when VPP e VPPL
This same subset of operations is also available
when high voltage is applied to the VPP pin In addi-
tion high voltage on VPP enables successful erasure
and programming of the device All functions associ-
ated with
altering memory contentsprogram
erase status and inteligent Identifierare accessed
via the Command Register and verified through the
Status Register
Commands are written using standard microproces-
sor write timings Register contents serve as input to
the WSM which controls the erase and program-
ming circuitry Write cycles also internally latch ad-
dresses and data needed for programming or erase
operations With the appropriate command written to
the register standard microprocessor read timings
output array data access the intelligent identifier
codes or output program and erase status for verifi-
cation
Interface software to initiate and poll progress of in-
ternal program and erase can be stored in any of the
28F001BX blocks This code is copied to and exe-
cuted from system RAM during actual flash memory
update
After successful completion of program
andor erase code execution out of the 28F001BX
is again possible via the Read Array command
Erase suspendresume capability allows system
software to suspend block erase and read dataexe-
cute code from any other block
Command Register and Write
Automation
An on-chip state machine controls block erase and
byte program freeing the system processor for other
tasks After receiving the erase setup and erase
confirm commands
the state machine controls
block pre-conditioning and erase returning progress
via the Status Register Programming is similarly
controlled after destination address and expected
data are supplied The program algorithm of past In-
tel Flash Memories is now regulated by the state
machine including program pulse repetition where
required and internal verification and margining of
data
Data Protection
Depending on the application the system designer
may choose to make the VPP power supply switcha-
ble (available only when memory updates are re-
quired) or hardwired to VPPH When VPP e VPPL
memory contents cannot be altered The 28F001BX
Command Register architecture provides protection
from unwanted program or erase operations even
when high voltage is applied to VPP Additionally all
functions are disabled whenever VCC is below the
write lockout voltage VLKO or when RP
is at VIL
The 28F001BX accommodates either design prac-
tice and encourages optimization of the processor-
memory interface
The two-step programerase write sequence to the
Command Register provides additional software
write protection
1FFFF
8-KByte BOOT BLOCK
1DFFF
1E000
4-KByte PARAMETER BLOCK
1CFFF
1D000
4-KByte PARAMETER BLOCK
1BFFF
1C000
112-KByte MAIN BLOCK
00000
Figure 7 28F001BX-T Memory Map
1FFFF
112-KByte MAIN BLOCK
03FFF
04000
4-KByte PARAMETER BLOCK
02FFF
03000
4-KByte PARAMETER BLOCK
01FFF
02000
8-KByte BOOT BLOCK
00000
Figure 8 28F001BX-B Memory Map
6


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