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MC146805E2CFN bảng dữ liệu(PDF) 11 Page - InnovASIC, Inc |
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MC146805E2CFN bảng dữ liệu(HTML) 11 Page - InnovASIC, Inc |
11 / 31 page IA6805E2 Data Sheet Microprocessor Unit As of Production Version 00 Copyright © 2002 ENG21108140100 www.innovasic.com innovASIC Customer Support: The End of Obsolescence ™ Page 11 of 31 1-888-824-4184 External Interrupt: If the external interrupt pin irq_n is “low” and the interrupt mask bit of the condition code register is cleared, the external interrupt occurs. When the interrupt is recognized, the current state of the machine is pushed onto the stack and the condition code register I-bit gets set masking further interrupts until the present one is serviced. The program counter is then loaded with the contents of the interrupt vector, which contains the location of the interrupt service routine. The contents of $1FFA and $1FFB specify the address for this service routine. A functional diagram of the external interrupt is shown in Figure 9 and a mode diagram of the external interrupt is shown in Figure 10. The timing diagram shows two different treatments of the interrupt line (irq_n) to the processor. The first shows several interrupt lines “wire ORed” to form the interrupts at the processor. If the interrupt line (irq_n) remains low after servicing an interrupt, the next interrupt is recognized. The second shows single pulses on the interrupt line spaced far enough apart to be serviced. The minimum time between pulses is a function of the length of the interrupt service. After a pulse occurs, the next pulse should not occur until an RTI has occurred. The time between pulses (t ILIL) is obtained by adding 20 instruction cycles to the total number of cycles it takes to complete the service routine including the RTI instruction. D C Q Q R VDD INTERRUPT PIN POWER-ON RESET EXTERNAL INTERRUPT BEING SERVICED EXTERNAL RESET I BIT (CCR) EXTERNAL INTERUPT REQUEST Figure 9. Interrupt Functional Diagram |
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