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AD1877 bảng dữ liệu(PDF) 11 Page - Analog Devices |
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AD1877 bảng dữ liệu(HTML) 11 Page - Analog Devices |
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11 / 20 page  AD1877 REV. A –11– Two modes deserve special discussion. The first special mode, “Slave Mode, Data Position Controlled by WCLK Input” (S/M = HI, RLJUST = HI, MSBDLY = LO), shown in Figure 8, is the only mode in which WCLK is an input. The 16-bit output data words can be placed at user-defined locations within 32-bit fields. The MSB will appear in the BCLK period after WCLK is detected HI by the BCLK sampling edge. If WCLK is HI dur- ing the first BCLK of the 32-bit field (if WCLK is tied HI for example), then the MSB of the output word will be valid on the sampling edge of the second BCLK. The effect is to delay the MSB for one bit clock cycle into the field, making the output data compatible at the data format level with the I 2S data for- mat. Note that the relative placement of the WCLK input can vary from 32-bit field to 32-bit field, even within the same 64-bit frame. For example, within a single 64-bit frame, the left word could be right justified (by pulsing WCLK HI on the 16th BCLK) and the right word could be in an I 2S-compatible data format (by having WCLK HI at the beginning of the second field). In the second special mode “Master Mode, Right-Justified with MSB Delay, WCLK Pulsed in 17th Cycle” (S/M = LO, RLJUST = HI, MSBDLY = LO), shown in Figure 12, WCLK is an output and is pulsed for one cycle by the AD1877. The MSB is valid on the 18th BCLK sampling edge, and the LSB extends into the first BCLK period of the next 32-bit field. Timing Parameters For master modes, a BCLK transmitting edge (labeled “XMIT”) will be delayed from a CLKIN rising edge by tDLYCKB, as shown in Figure 17. A LRCK transition will be delayed from a BCLK transmitting edge by tDLYBLR. A WCLK rising edge will be delayed from a BCLK transmitting edge by tDLYBWR, and a WCLK falling edge will be delayed from a BCLK transmitting edge by tDLYBWF. The DATA and TAG outputs will be delayed from a transmitting edge of BCLK by tDLYDT. For slave modes, an LRCK transition must be setup to a BCLK sampling edge (labeled “SAMPLE”) by tSETLRBS. The DATA and TAG outputs will be delayed from an LRCK transition by tDLYLRDT, and DATA and TAG outputs will be delayed from BCLK transmitting edge by tDLYBDT. For “Slave Mode, Data Position Controlled by WCLK Input,” WCLK must be setup to a BCLK sampling edge by tSETWBS. For both master and slave modes, BCLK must have a minimum LO pulsewidth of tBPWL, and a minimum HI pulsewidth of tBPWH. The AD1877 CLKIN and RESET timing is shown in Figure 19. CLKIN must have a minimum LO pulsewidth of tCPWL, and a minimum HI pulse width of tCPWH. The minimum period of CLKIN is given by tCLKIN. RESET must have a minimum LO pulsewidth of tRPWL. Note that there are no setup or hold time requirements for RESET. Synchronizing Multiple AD1877s Multiple AD1877s can be synchronized by making all the AD1877s serial port slaves. This option is illustrated in Figure 6. See the “Reset, Autocalibration and Power Down” section above for additional information. #1 AD1877 SLAVE MODE CLKIN DATA BCLK WCLK L RCK CLOCK SOURCE #2 AD1877 SLAVE MODE CLKIN DATA BCLK WCLK L RCK #N AD1877 SLAVE MODE CLKIN DATA BCLK WCLK L RCK RESET RESET RESET Figure 6. Synchronizing Multiple AD1877s |
Số phần tương tự - AD1877_15 |
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Mô tả tương tự - AD1877_15 |
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