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AD676 bảng dữ liệu(PDF) 4 Page - Analog Devices

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AD676
REV. A
–4–
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Units
Conversion Time
2
tC
10
1000
µs
CLK Period
3
tCLK
480
ns
Calibration Time
tCT
85,530
tCLK
Sampling Time (Included in tC)tS
2
µs
CAL to BUSY Delay
tCALB
75
150
ns
BUSY to SAMPLE Delay
tBS
2
µs
SAMPLE to BUSY Delay
tSB
15
100
ns
CLK HIGH
4
tCH
50
ns
CLK LOW
4
tCL
50
ns
SAMPLE LOW to 1st CLK Delay
tSC
50
ns
SAMPLE LOW
tSL
100
ns
Output Delay
tOD
125
200
ns
Status Delay
tSD
50
ns
CAL HIGH Time
tCALH
50
ns
NOTES
1See the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing.
2Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion time is specified to account for the droop of the
internal sample/hold function. Longer conversion times may degrade performance. See “General Conversion Guidelines” for additional explanation of maximum con-
version time.
3580 ns is recommended for optimal accuracy over temperature.
4t
CH + tCL = tCLK and must be greater than 480 ns.
CAL
BUSY
CLK
t
CH
t
CL
t
CLK
tCALB
t
OD
t
CT
CALH
t
Figure 1. Calibration Timing
SAMPLE
(INPUT)
CLK
(INPUT)
BIT 1 – BIT 16
(OUTPUTS)
BUSY
(OUTPUT)
1
234
5
t
S
t
SL
t
SC
t
CLK
t
CL
t
CH
t
OD
t
SD
t
SB
t
BS
t
C
13
14
15
16
17
(PREVIOUS CONVERSION)
(NEW DATA)
Figure 2a. General Conversion Timing
SAMPLE
(INPUT)
CLK
(INPUT)
BIT 1 – BIT 16
(OUTPUTS)
BUSY
(OUTPUT)
1
234
5
t
S
t
SL
t
SC
t
CLK
t
CL
t
CH
t
OD
t
SD
t
SB
t
BS
t
C
13
14
15
16
17
t
S
(PREVIOUS CONVERSION)
(NEW DATA)
Figure 2b. Continuous Conversion Timing
(TMIN to TMAX VCC = +12 V
5%, VEE = –12 V
5%, VDD = +5 V
10%, VREF = 10.0 V)
1


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