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AD607 bảng dữ liệu(PDF) 4 Page - Analog Devices |
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AD607 bảng dữ liệu(HTML) 4 Page - Analog Devices |
4 / 24 page REV. C –4– AD607 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Reads Function 1 FDIN Frequency Detector Input PLL Input for I/Q Demodulator Quadrature Oscillator, ±400 mV Drive Required from External Oscillator. Must be biased at VP/2. 2 COM1 Common #1 Supply Common for RF Front End and Main Bias 3 PRUP Power-Up Input 3 V/5 V CMOS compatible power-up control; logical high = powered-up; max input level = VPS1 = VPS2. 4 LOIP Local Oscillator Input LO input, ac-coupled ±54 mV LO input is required (–16 dBm for 50 Ω input termination). 5 RFLO RF “Low” Input Usually Connected to AC Ground 6 RFHI RF “High” Input AC-Coupled, ±56 mV, Max RF Input for Linear Operation 7 GREF Gain Reference Input High Impedance Input, typically 1.5 V, sets gain scaling. 8 MXOP Mixer Output High Impedance, Single-Sided Current Output, ±1.3 V Max Voltage Output ( ±6 mA Max Current Output) 9 VMID Midsupply Bias Voltage Output of the Midsupply Bias Generator (VMID = VPOS/2) 10 IFHI IF “High” Input AC-Coupled IF Input, ±56 mV Max Input for Linear Operation 11 IFLO IF “Low” Input Reference Node for IF Input; Auto-Offset Null 12 GAIN Gain Control Input High Impedance Input, 0 V–2 V Using 3 V Supply, Max Gain at V = 0 13 COM2 Common #2 Supply Common for IF Stages and Demodulator 14 IFOP IF Output Low Impedance, Single-Sided Voltage Output, 5 dBm ( ±560 mV) Max 15 DMIP Demodulator Input Signal input to I and Q demodulators has a ±150 mV max input at IF > 3 MHz for linear operation; ±75 mV max input at IF < 3 MHz for linear operation. Must be biased at VP/2. 16 VPS2 VPOS Supply #2 Supply to High Level IF, PLL, and Demodulators 17 QOUT Quadrature Output Low Impedance Q Baseband Output; ±1.23 V Full Scale in 20 kΩ Min Load; AC-Coupled 18 IOUT In-Phase Output Low Impedance I Baseband Output; ±1.23 V Full Scale in 20 kΩ Min Load; AC-Coupled 19 FLTR PLL Loop Filter Series RC PLL Loop Filter, Connected to Ground 20 VPS1 VPOS Supply #1 Supply to Mixer, Low Level IF, PLL, and Gain Control PIN CONNECTION 20-Lead SSOP (RS-20) 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 TOP VIEW (Not to Scale) AD607 FDIN QOUT IOUT FLTR VPS1 COM1 PRUP LOIP IFOP DMIP VPS2 RFLO RFHI GREF MXOP VMID IFHI IFLO GAIN COM2 |
Số phần tương tự - AD607_15 |
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Mô tả tương tự - AD607_15 |
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