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LM98722 bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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LM98722 bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 20 page LM98722 www.ti.com SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 Electrical Characteristics (continued) The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. Parameter Test Conditions Min(1) Typ(2) Max(1)(3) Units Digital Offset “DAC” Specifications Resolution 7 Bits Digital Offset DAC LSB Step Size Referred to AFE Output 32 LSB Offset Adjustment Range Min DAC Code =7b0000000 -2048 Referred to AFE Output Mid DAC Code =7b1000000 0 LSB Max DAC Code = 7b1111111 +2016 Full Channel Performance Specifications DNL Differential Non-Linearity See (4) -0.999 +0.8/-0.7 2.5 LSB INL Integral Non-Linearity See (4) -75 +18/-25 75 LSB Minimum PGA Gain(4) -76 dB 10 26 LSB RMS SNR Total Output Noise Maximum PGA Gain(4) -56 dB 96 LSB RMS Channel to Channel Crosstalk Mode 3 26 LSB Mode 2 17 (4) This parameter ensured by design and characterization. AC Timing Specifications The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. (1) Parameter Test Conditions Min(2) Typ(3) Max(2) Units Input Clock Timing Specifications INCLK = PIXCLK 0.66 15 (Mode 3) (Pixel Rate Clock) 1 22.5 (Mode 2) MHz 1 22.5 (Mode 1) fINCLK Input Clock Frequency INCLK = ADCCLK 45 (Mode 3) (ADC Rate Clock) 2 45 (Mode 2) MHz 22.5 (Mode 1) Tdc Input Clock Duty Cycle 40/60 50/50 60/40 % Full Channel Latency Specifications 3 Channel Mode Pipeline Delay PIXPHASE0 24 PIXPHASE1 23 1/2 tLAT3 TADC PIXPHASE2 23 PIXPHASE3 22 1/2 2 Channel Mode Pipeline Delay PIXPHASE0 21 PIXPHASE1 20 1/2 tLAT2 TADC PIXPHASE2 20 PIXPHASE3 19 1/2 (1) The analog inputs are protected as shown in Figure 4. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per Note 4 under the Absolute Maximum Ratings Table. However, input errors will be generated If the input goes above VA and below AGND. (2) Test limits are ensured to TI's AOQL (Average Outgoing Quality Level). (3) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM98722 |
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