công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADC78H89CIMT bảng dữ liệu(PDF) 5 Page - Texas Instruments |
|
ADC78H89CIMT bảng dữ liệu(HTML) 5 Page - Texas Instruments |
5 / 23 page ADC78H89 www.ti.com SNAS201D – APRIL 2003 – REVISED MARCH 2013 ADC78H89 CONVERTER ELECTRICAL CHARACTERISTICS (1) (continued) The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, fSCLK = 8 MHz, fSAMPLE = 500 KSPS unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits Units (2) POWER SUPPLY CHARACTERISTICS (CL = 10 pF) (3) 2.7 V (min) AVDD, Analog and Digital Supply Voltages AVDD ≥ DVDD DVDD 5.25 V (max) AVDD = DVDD = +4.75V to +5.25V, 1.65 2.3 mA (max) fSAMPLE = 500 KSPS, fIN = 40 kHz Total Supply Current, Normal Mode (Operational, CS low) AVDD = DVDD = +2.7V to +3.6V, 0.5 2.3 mA (max) fSAMPLE = 500 KSPS, fIN = 40 kHz IDD AVDD = DVDD = +4.75V to +5.25V, 0.1 µA fSAMPLE = 0 KSPS Total Supply Current, Shutdown (CS high) AVDD = DVDD = +2.7V to +3.6V, 0.1 µA fSAMPLE = 0 KSPS AVDD = DVDD = +4.75V to +5.25V 8.3 12 mW (max) Power Consumption, Normal Mode (Operational, CS low) AVDD = DVDD = +2.7V to +3.6V 1.5 8.3 mW (max) PD AVDD = DVDD = +4.75V to +5.25V 0.5 µW Power Consumption, Shutdown (CS high) AVDD = DVDD = +2.7V to +3.6V 0.3 µW AC ELECTRICAL CHARACTERISTICS fSCLK Maximum Clock Frequency 8 MHz (max) Minimum Clock Frequency 50 kHz fS Maximum Sample Rate 500 KSPS (min) tCONV Conversion Time 13 13 SCLK cycles 40 % (min) DC Duty Cycle 50 60 % (max) tACQ Track/Hold Acquisition Time Full-Scale Step Input 3 SCLK cycles Throughput Time Conversion Time + Acquisition Time 16 SCLK cycles fRATE Throughput Rate 500 KSPS (min) tAD Aperture Delay 4 ns (3) Except power supply pins. ADC78H89 TIMING SPECIFICATIONS The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, fSCLK = 8 MHz, CL = 50 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits Units t1a SCLK High to CS Fall Setup Time See (1) 10 ns (min) t1b SCLK Low to CS Fall Hold Time See (1) 10 ns (min) t2 Delay from CS Until DOUT TRI-STATE™ Disabled 30 ns (max) t3 Data Access Time after SCLK Falling Edge 30 ns (max) t4 Data Setup Time Prior to SCLK Rising Edge 10 ns (max) t5 Data Valid SCLK Hold Time 10 ns (max) t6 SCLK High Pulse Width 0.4 x tSCLK ns (min) t7 SCLK Low Pulse Width 0.4 x tSCLK ns (min) t8 CS Rising Edge to DOUT High-Impedance 20 ns (max) (1) Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by t1a and t1b. Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC78H89 |
Số phần tương tự - ADC78H89CIMT |
|
Mô tả tương tự - ADC78H89CIMT |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |