công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADS8508IBDWR bảng dữ liệu(PDF) 5 Page - Texas Instruments |
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ADS8508IBDWR bảng dữ liệu(HTML) 5 Page - Texas Instruments |
5 / 28 page www.ti.com TIMING REQUIREMENTS, T A = –40°C to 85°C VDIG VANA BUSY CS R/C TAG DATA DATACLK SYNC R1IN AGND1 REF CAP AGND2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DW PACKAGE R2IN R3IN SB/BTC EXT/INT DGND PWRD (TOP VIEW) ADS8508 SLAS433 – SEPTEMBER 2005 PARAMETER MIN TYP MAX UNIT tw1 Pulse duration, convert 40 ns td1 Delay time, BUSY from R/C low 6 20 ns tw2 Pulse duration, BUSY low 2.2 µs td2 Delay time, BUSY, after end of conversion 5 ns td3 Delay time, aperture 5 ns tconv Conversion time 2.2 µs tacq Acquisition time 1.8 µs tconv + tacq Cycle time 4 µs td4 Delay time, R/C Low to internal DATACLK output 270 ns tc1 Cycle time, internal DATACLK 110 ns td5 Delay time, data valid to internal DATACLK high 15 35 ns td6 Delay time, data valid after internal DATACLK low 20 35 ns tc2 Cycle time, external DATACLK 35 ns tw3 Pulse duration, external DATACLK high 15 ns tw4 Pulse duration, external DATACLK low 15 ns tsu1 Setup time, R/C rise/fall to external DATACLK high 15 tC2 + 5 ns tsu2 Setup time, R/C transition to CS transition 10 ns td7 Delay time, SYNC, after external DATACLK high 3 35 ns td8 Delay time, data valid 2 20 ns td9 Delay time, CS to rising edge 10 ns td10 Delay time, previous data available after CS, R/C low 2 µs tsu3 Setup time, BUSY transition to first external DATACLK 5 ns td11 Delay time, final external DATACLK to BUSY falling edge 1 µs tsu3 Setup time, TAG valid 0 ns th1 Hold time, TAG valid 2 ns 5 |
Số phần tương tự - ADS8508IBDWR |
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Mô tả tương tự - ADS8508IBDWR |
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