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ADC12DL040CIVS bảng dữ liệu(PDF) 7 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter
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background image
VA
AGND
To Internal Circuitry
I/O
ADC12DL040
www.ti.com
SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On,
parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C
(1) (2) (3)
Typical
Limits
Units
Symbol
Parameter
Conditions
(4)
(4)
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12
Bits (min)
INL
Integral Non Linearity (5)
±0.8
± 2.6
LSB (max)
DNL
Differential Non Linearity
±0.3
+0.96, -0.9
LSB (max)
PGE
Positive Gain Error
±0.2
+2.5, -3.3
%FS (max)
NGE
Negative Gain Error
±0.2
±3.6
%FS (max)
TC GE
Gain Error Tempco
−40°C ≤ TA ≤ +85°C
5
ppm/°C
VOFF
Offset Error (VIN+ = VIN−)
0.1
±0.8
%FS (max)
TC VOFF
Offset Error Tempco
−40°C ≤ TA ≤ +85°C
3
ppm/°C
Under Range Output Code
0
0
Over Range Output Code
4095
4095
REFERENCE AND ANALOG INPUT CHARACTERISTICS
0.5
V (min)
VCM
Common Mode Input Voltage
1.5
2.0
V (max)
VRMA,
Reference Output Voltage
Output load = 1 mA
1.5
V
VRMB
(CLK LOW)
8
pF
CIN
VIN Input Capacitance (each pin to GND)
VIN = 2.5 Vdc + 0.7 Vrms
(CLK HIGH)
7
pF
0.8
V (min)
VREF
External Reference Voltage (6)
1.00
1.2
V (max)
Reference Input Resistance
1
M
Ω (min)
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
Full Power Bandwidth
0 dBFS Input, Output at
−3 dB
250
MHz
fIN = 1 MHz, VIN = −0.5 dBFS
69
dB
SNR
Signal-to-Noise Ratio
fIN = 10 MHz, VIN = −0.5 dBFS
69
67.5
dB (min)
fIN = 20 MHz, VIN = −0.5 dBFS
68.5
66.5
dB
(1)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above
VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate
conversions.
(2)
To specify accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(3)
With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.
(4)
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
(5)
Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through
positive and negative full-scale.
(6)
Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ (SOT-23
package) is recommended for external reference applications.
Copyright © 2005–2013, Texas Instruments Incorporated
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