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Package/Ordering Information

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

DISSIPATION RATINGS TABLE

ADS1208

SBAS348A – MARCH 2005 – REVISED MARCH 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated

circuits be handled with appropriate precautions. Failure to observe proper handling and installation

procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision

integrated circuits may be more susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or see the TI web site at www.ti.com.

ADS1208I

UNIT

–0.3 to +6

V

–0.3 to +6

V

Analog input voltage with respect to AGND

V

Reference input voltage with respect to AGND

V

Digital input voltage with respect to BGND

V

Ground voltage difference AGND to BGND

±0.3

V

Input current to any pin except supply

±10

mA

Power dissipation

See Dissipation Ratings Table

–40 to +150

°C

–40 to +85

°C

–65 to +150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PARAMETER

MIN

NOM

MAX

UNIT

4.5

5.0

5.5

V

Low-voltage levels

2.7

3.6

V

5V logic levels

4.5

5.0

5.5

V

Reference input voltage

0.5

2.5

3.0

V

Analog inputs

V

DERATING FACTOR

BOARD

PACKAGE

POWER RATING

POWER RATING

POWER RATING

PW

35°C/W

147°C/W

6.8mW/°C

850mW

544mW

442mW

PW

33.6°C/W

108.4°C

9.225W/°C

1150mW

738mW

600mW

(1)

The JEDEC low-K (1s) board used to derive this data was a 3in x 3in, two-layer board with 2-ounce copper traces on top of the board.

(2)

The JEDEC high-K (2s2p) board used to derive this data was a 3in x 3in, multilayer board with 1-ounce internal power and ground

planes and 2-ounce copper traces on top and bottom of the board.

2