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ADC122S655CIMMX bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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ADC122S655CIMMX bảng dữ liệu(HTML) 7 Page - Texas Instruments |
7 / 28 page DOUT CS VIH tDIS 90% 10% 90% 10% DOUT 90% 10% SCLK CS tCSSU 1 2 ADC122S655 www.ti.com SNAS445A – FEBRUARY 2008 – REVISED MARCH 2013 Figure 5. Valid CS Assertion Times Figure 6. Voltage Waveform for tDIS Specification Definitions APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is acquired or held for conversion. COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed from 2V to 3V. CMRR = 20 LOG ( Δ Output Offset / Δ Common Input) (1) CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC122S655 is specified not to have any missing codes. NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions from negative full scale to the next code and −VREF + 0.5 LSB. NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error. OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from code 000h to 001h and 1/2 LSB. POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions to positive full scale and VREF minus 1.5 LSB. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADC122S655 |
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