ADS7812

11

SBAS042A

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might be possible to use the rising edge of the DATACLK

signal. However, one extra clock period (not shown in

Figures 6, 7, and 8) is needed for the final bit.

The external DATACLK signal must be LOW or CS must

8). If this is not observed, the output shift register of the

ADS7812 will not be updated with the conversion result.

Instead, the previous contents of the shift register will

remain and the new result will be lost.

If more than 12 clock cycles are provided to the DATACLK

input, the DATA output will go LOW after the rising edge

of the 13th clock period. The operation of the ADS7812 will

not be affected as long as the timing specifications are met.

Before reading the next three paragraphs, consult the Sensi-

tivity to External Digital Signals section of this data sheet.

This will explain many of the concerns regarding how and

when to apply the external DATACLK signal.

External DATACLK Active After the Conversion

The preferred method of obtaining the conversion result is to

provide the DATACLK signal after the conversion has been

completed and before the next conversion starts—as shown

in Figure 6. Note that the DATACLK signal should be static

before the start of the next conversion. If this is not ob-

served, the DATACLK signal could affect the voltage that

is acquired.

External DATACLK Active During the Next Conversion

Another method of obtaining the conversion result is shown

in Figure 7. Since the output shift register is not updated until

the end of the conversion, the previous result remains valid

during the next conversion. If a fast clock (

≥ 2MHz) can be

provided to the ADS7812, the result can be read during time

less likely to affect the conversion result.

FIGURE 7. Serial Data Timing, External Clock, Clocking During the Next Conversion (EXT/INT HIGH,

CS LOW).

FIGURE 8. Serial Data Timing, External Clock, Clocking After the Conversion Completes and During the Next Conversion

(EXT/INT HIGH, CS LOW).

BUSY

CONV

t

24

t

4

t

5

DATACLK

t

25

1

2

n

n+1

11

12

DATA

MSB

Bit 10

Bit n

Bit n-1

Bit 1

LSB

34

BUSY

CONV

t

2

t

1

DATACLK

t

24

t

25

t

23

t

22

t

21

t

20

t

19

1

1

211

12

DATA

MSB

Bit 10

Bit 9

Bit 1

LSB

MSB