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ADS7824 bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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ADS7824 bảng dữ liệu(HTML) 3 Page - Texas Instruments |
3 / 22 page 3 ® ADS7824 SPECIFICATIONS (CONT) ELECTRICAL At T A = –40 °C to +85°C, f S = 40kHz, V S1 = V S2 = V S = +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified. ADS7824P, U ADS7824PB, UB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS DIGITAL TIMING Bus Access Time PAR/SER = +5V 83 T ns Bus Relinquish Time PAR/SER = +5V 83 T ns Data Clock PAR/SER = 0V Internal Clock (Output only when EXT/INT LOW 0.5 1.5 TT MHz transmitting data) External Clock EXT/INT HIGH 0.1 10 TT MHz POWER SUPPLIES VS1 = VS2 = VS +4.75 +5 +5.25 TT T V Power Dissipation fS = 40kHz 50 T mW PWRD HIGH 50 T µW TEMPERATURE RANGE Specified Performance –40 +85 TT °C Storage –65 +150 TT °C Thermal Resistance ( θ JA) Plastic DIP 75 T °C/W SOIC 75 T °C/W NOTES: (1) An asterik (T) specifies same value as grade to the left. (2) LSB means Least Significant Bit. For the 12-bit, ±10V input ADS7824, one LSB is 4.88mV. (3) Typical rms noise at worst case transitions and temperatures. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) A full scale sinewave input on one channel will be attenuated by this amount on the other channels. (7) Useable Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. (8) The ADS7824 will accurately acquire any input step if given a full acquisition period after the step. (9) Recovers to specified performance after 2 x FS input overvoltage, and normal acquisitions can begin. PIN CONFIGURATION ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS Analog Inputs: AIN0, AIN1, AIN2, AIN3 .............................................. ±15V REF ................................... (AGND2 –0.3V) to (VS + 0.3V) CAP ........................................ Indefinite Short to AGND2, Momentary Short to VS VS1 and VS2 to AGND2 ........................................................................... 7V VS1 to VS2 .......................................................................................... ±0.3V Difference between AGND1, AGND2 and DGND ............................. ±0.3V Digital Inputs and Outputs .......................................... –0.3V to (VS + 0.3V) Maximum Junction Temperature ..................................................... 150 °C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ................................................ +300 °C Maximum Input Current to Any Pin ................................................. 100mA PACKAGE MINIMUM SIGNAL- DRAWING TEMPERATURE MAXIMUM INTEGRAL TO-(NOISE + DISTORTION) PRODUCT PACKAGE NUMBER(1) RANGE LINEARITY ERROR (LSB) RATIO (dB) ADS7824P Plastic Dip 246 –40 °C to +85°C ±170 ADS7824PB Plastic Dip 246 –40 °C to +85°C ±0.5 72 ADS7824U SOIC 217 –40 °C to +85°C ±170 ADS7824UB SOIC 217 –40 °C to +85°C ±0.5 72 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION Top View DIP/SOIC V S1 V S2 PWRD CONTC BUSY CS R/C BYTE PAR/SER A0 A1 D0 D1 D2 AGND1 AIN 0 AIN 1 AIN 2 AIN 3 CAP REF AGND2 D7 D6 D5 D4 D3 DGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ADS7824 TRI-STATE TRI-STATE TRI-STATE EXT/INT SYNC TAG SDATA DATACLK |
Số phần tương tự - ADS7824_14 |
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Mô tả tương tự - ADS7824_14 |
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