1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ADS8515

+5V

+

+

+

+

Convert Pulse

40 ns Min

2.2

µF

0.1

µF

10

µF

D15 (MSB)

D14

D13

D12

D11

D10

D9

D8

D0 (LSB)

D1

D2

D3

D4

D5

D6

D7

2.2

µF

BUSY

R/C

ADS8515

www.ti.com

SLAS460D – JUNE 2007 – REVISED SEPTEMBER 2010

BASIC OPERATION

Figure 19 shows a basic circuit to operate the ADS8515 with a full parallel data output. Taking R/C (pin 24) low

for a minimum of 40 ns initiates a conversion. BUSY (pin 26) goes low and stays low until the conversion is

completed and the output registers are updated. Data are output in binary twos complement with the MSB on pin

6. BUSY going high can be used to latch the data.

The ADS8515 begins tracking the input signal at the end of the conversion. Allowing 4 ms between convert

commands assures accurate acquisition of a new signal.

Figure 19. Basic Operation

Copyright © 2007–2010, Texas Instruments Incorporated

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