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ADS8515IBDBR bảng dữ liệu(PDF) 11 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  16-Bit 250-kSPS Sampling CMOS ANALOG-TO-DIGITAL CONVERTER
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ADS8515IBDBR bảng dữ liệu(HTML) 11 Page - Texas Instruments

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Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 15 (MSB)
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
ADS8515
BYTE LOW
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15 (MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
ADS8515
BYTE HIGH
+5 V
ADS8515
www.ti.com
SLAS460D – JUNE 2007 – REVISED SEPTEMBER 2010
PARALLEL OUTPUT (After a Conversion)
After conversion n is completed and the output registers have been updated, BUSY (pin 26) goes high. Valid
data from conversion n are available on D15 to D0 (pins 6 to 13 and 15 to 22). BUSY going high can be used to
latch the data. Refer to Table 3 and Figure 21, Figure 22, and Figure 23 for timing specifications.
PARALLEL OUTPUT (During a Conversion)
After conversion n has been initiated, valid data from conversion –1 can be read and are valid up to t2 after the
start of conversion n. Do not attempt to read data from t2 after the start of conversion n until BUSY (pin 26) goes
high; this may result in reading invalid data. Refer to Table 3 and Figure 21, Figure 22, and Figure 23 for timing
specifications.
Note: For the best possible performance, data should not be read during a conversion. The switching noise of
the asynchronous data transfer can cause digital feedthrough degrading the converter performance.
The number of control lines can be reduced by tying CS low while using the falling edge of R/C to initiate
conversions and the rising edge of R/C to activate the output mode of the converter. See Figure 21.
Table 3. Conversion Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tw1
Pulse duration, convert
40
ns
ta
Access time, data valid after R/C low
0.8
1.2
ms
tpd
Propagation delay time, BUSY from R/C low
6
20
ns
tw2
Pulse duration, BUSY low
2
ms
td1
Delay time, BUSY after end of conversion
5
ns
td2
Delay time, aperture
5
ns
tconv
Conversion time
2
ms
tacq
Acquisition time
2
ms
tdis
Disable time, bus
10
15
83
ns
td3
Delay time, BUSY after data valid
35
50
ns
tv
Valid time, previous data remains valid after R/C low
1.5
2
ms
tconv + tacq
Throughput time
4
ms
tsu
Setup time, R/C to CS
10
ns
tc
Cycle time between conversions
4
ms
ten
Enable time, bus
10
15
30
ns
td4
Delay time, BYTE
10
15
30
ns
Figure 20. Bit Locations Relative to State of BYTE (Pin 23)
Copyright © 2007–2010, Texas Instruments Incorporated
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