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ADS8555SPM bảng dữ liệu(PDF) 9 Page - Texas Instruments |
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ADS8555SPM bảng dữ liệu(HTML) 9 Page - Texas Instruments |
9 / 37 page ADS8555 www.ti.com SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 PIN DESCRIPTIONS (continued) DESCRIPTION NAME PIN # TYPE(1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) Analog input of channel B0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 CH_B0 39 AI (RANGE_B) in software mode. Analog input of channel B1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 CH_B1 42 AI (RANGE_B) in software mode. Analog input of channel C0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 CH_C0 45 AI (RANGE_C) in software mode. Analog input of channel C1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 CH_C1 48 AI (RANGE_C) in software mode. Reference voltage input/output (0.5V to 3.025V). The internal reference is enabled via REFEN/WR pin in hardware mode or CR bit C25 (REFEN) in software mode. REFIO 51 AIO The output value is controlled by the internal DAC (CR bits C[9:0]). Connect a 470nF ceramic decoupling capacitor between this pin and pin 52. Decoupling capacitor for reference of channels A. REFC_A 54 AI Connect a 10 μF ceramic decoupling capacitor between this pin and pin 53. Decoupling capacitor for reference of channels B. REFC_B 56 AI Connect a 10 μF ceramic decoupling capacitor between this pin and pin 55. Decoupling capacitor for reference of channels C. REFC_C 58 AI Connect a 10 μF ceramic decoupling capacitor between this pin and pin 57. Interface mode selection input. PAR/SER 61 DI When low, the parallel interface is selected. When high, the serial interface is enabled. Mode selection input. HW/SW 62 DI When low, the hardware mode is selected and part works according to the settings of external pins. When high, the software mode is selected in which the device is configured by writing into the control register. Hardware mode (HW/SW = 0): Hardware mode (HW/SW = 0): Internal reference enable input. Internal reference enable input. When high, the internal reference is enabled (the When high, the internal reference is enabled (the reference reference buffers are to be enabled). When low, buffers are to be enabled). When low, the internal reference the internal reference is disabled and an external is disabled and an external reference should be applied at REFEN/WR 63 DI reference is applied at REFIO. REFIO. Software mode (HW/SW = 1): Write input. The parallel data input is enabled, when CS and Software mode (HW/SW = 1): Connect to BGND or BVDD. WR are low. The internal reference is enabled by The internal reference is enabled by CR bit C25 (REFEN). the CR bit C25 (REFEN). DB15 64 DIO Data bit 15 (MSB) input/output Connect to BGND © 2010–2011, Texas Instruments Incorporated 9 Product Folder Link(s): ADS8555 |
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