APPLICATION INFORMATION

Logic Inputs

Analog Signal Levels

Layout

TS3A4751

Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum

ratings because stresses beyond the listed ratings can cause permanent damage to the devices. Always

Although it is not required, power-supply bypassing improves noise margin and prevents switching noise

adequate for most applications.

The TS3A4751 logic inputs can be driven up to 3.6 V, regardless of the supply voltage. For example, with a

1.8-V supply, IN may be driven low to GND and high to 3.6 V. Driving IN rail to rail minimizes power

consumption.

(see Typical Operating Characteristics). The switches are bidirectional, so NO and COM can be used as either

inputs or outputs.

High-speed switches require proper layout and design procedures for optimum performance. Reduce stray

inductance and capacitance by keeping traces short and wide. Ensure that bypass capacitors are as close to the

device as possible. Use large ground planes where possible.

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