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ADS1204IRHBR bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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ADS1204IRHBR bảng dữ liệu(HTML) 8 Page - Texas Instruments |
8 / 29 page PARAMETER MEASUREMENT INFORMATION CLKOUT OUTx t C1 t W2 t D4 t D3 t C2 t W1 t D1 t D2 CLKIN TIMING REQUIREMENTS: 5.0V (1) TIMING REQUIREMENTS: 3.0V (1) ADS1204 SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009........................................................................................................................................... www.ti.com Figure 1. ADS1204 Timing Diagram Over recommended operating free-air temperature range at –40°C to +105°C, AVDD = 5V, and BVDD = 5V, unless otherwise noted. PARAMETER MIN MAX UNIT tC1 CLKIN period 41.6 1000 ns tW1 CLKIN high time 10 tC1 – 10 ns tC2 CLKOUT period using internal oscillator (CLKSEL = 1) 83 125 ns CLKOUT period using external clock (CLKSEL = 0) 2 × tC1 ns tW2 CLKOUT high time (tC2/2) – 5 (tC2/2) + 5 ns tD1 CLKOUT rising edge delay after CLKIN rising edge 0 10 ns tD2 CLKOUT falling edge delay after CLKIN rising edge 0 10 ns tD3 Data valid delay after rising edge of CLKOUT (CLKSEL = 1) (tC2/4) – 8 (tC2/4) + 8 ns tD4 Data valid delay after rising edge of CLKOUT (CLKSEL = 0) tW1 – 3 tW1 + 7 ns (1) Applicable for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 1. Over recommended operating free-air temperature range at –40°C to +105°C, AVDD = 5V, and BVDD = 5V, unless otherwise noted. PARAMETER MIN MAX UNIT tC1 CLKIN period 41.6 1000 ns tW1 CLKIN high time 10 tC1 – 10 ns tC2 CLKOUT period using internal oscillator (CLKSEL = 1) 83 125 ns CLKOUT period using external clock (CLKSEL = 0) 2 × tC1 ns tW2 CLKOUT high time (tC2/2) – 5 (tC2/2) + 5 ns tD1 CLKOUT rising edge delay after CLKIN rising edge 0 10 ns tD2 CLKOUT falling edge delay after CLKIN rising edge 0 10 ns tD3 Data valid delay after rising edge of CLKOUT (CLKSEL = 1) (tC2/4) – 8 (tC2/4) + 8 ns tD4 Data valid delay after rising edge of CLKOUT (CLKSEL = 0) tW1 – 3 tW1 + 7 ns (1) Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 1. 8 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): ADS1204 |
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