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LM2757 bảng dữ liệu(PDF) 11 Page - Texas Instruments

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LM2757
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SNVS536D – OCTOBER 2007 – REVISED AUGUST 2009
For most applications, ceramic capacitors with an X7R or X5R temperature characteristic are preferred for use
with the LM2757. These capacitors have tight capacitance tolerance (as good as ±10%) and hold their value over
temperature (X7R: ±15% over -55ºC to 125ºC; X5R: ±15% over -55ºC to 85ºC).
Capacitors with a Y5V or Z5U temperature characteristic are generally not recommended for use with the
LM2757. These types of capacitors typically have wide capacitance tolerance (+80%, -20%) and vary
significantly over temperature (Y5V: +22%, -82% over -30ºC to +85ºC range; Z5U: +22%, -56% over +10ºC to
+85ºC range). Under some conditions, a 1µF-rated Y5V or Z5U capacitor could have a capacitance as low as
0.1µF. Such detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet the minimum
capacitance requirements of the LM2757.
Net capacitance of a ceramic capacitor decreases with increased DC bias. This degradation can result in lower
capacitance than expected on the input and/or output, resulting in higher ripple voltages and currents. Using
capacitors at DC bias voltages significantly below the capacitor voltage rating will usually minimize DC bias
effects. Consult capacitor manufacturers for information on capacitor DC bias characteristics.
Capacitance characteristics can vary quite dramatically with different application conditions, capacitor types, and
capacitor manufacturers. It is strongly recommended that the LM2757 circuit be thoroughly evaluated early in the
design-in process with the mass-production capacitors of choice. This will help ensure that any such variability in
capacitance does not negatively impact circuit performance.
The voltage rating of the output capacitor should be 10V or more. For example, a 10V 0603 1.0µF is acceptable
for use with the LM2757, as long as the capacitance does not fall below a minimum of 0.5µF in the intended
application. All other capacitors should have a voltage rating at or above the maximum input voltage of the
application. The capacitors should be selected such that the capacitance on the input does not fall below 0.7µF,
and the capacitance of the flying capacitors does not fall below 0.2µF.
The table below lists some leading ceramic capacitor manufacturers.
Manufacturer
Contact Information
AVX
www.avx.com
Murata
www.murata.com
Taiyo-Yuden
www.t-yuden.com
TDK
www.component.tdk.com
Vishay-Vitramon
www.vishay.com
OUTPUT CAPACITOR AND OUTPUT VOLTAGE RIPPLE
The output capacitor in the LM2757 circuit (COUT) directly impacts the magnitude of output voltage ripple. Other
prominent factors also affecting output voltage ripple include input voltage, output current and flying capacitance.
Due to the complexity of the regulation topology, providing equations or models to approximate the magnitude of
the ripple can not be easily accomplished. But one important generalization can be made: increasing
(decreasing) the output capacitance will result in a proportional decrease (increase) in output voltage ripple.
In typical high-current applications, a 1.0µF low-ESR ceramic output capacitor is recommended. Different output
capacitance values can be used to reduce ripple, shrink the solution size, and/or cut the cost of the solution. But
changing the output capacitor may also require changing the flying capacitor and/or input capacitor to maintain
good overall circuit performance. Performance of the LM2757 with different capacitor setups in discussed in the
section Recommended Capacitor Configurations.
High ESR in the output capacitor increases output voltage ripple. If a ceramic capacitor is used at the output, this
is usually not a concern because the ESR of a ceramic capacitor is typically very low and has only a minimal
impact on ripple magnitudes. If a different capacitor type with higher ESR is used (tantalum, for example), the
ESR could result in high ripple. To eliminate this effect, the net output ESR can be significantly reduced by
placing a low-ESR ceramic capacitor in parallel with the primary output capacitor. The low ESR of the ceramic
capacitor will be in parallel with the higher ESR, resulting in a low net ESR based on the principles of parallel
resistance reduction.
Copyright © 2007–2009, Texas Instruments Incorporated
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