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LM2743 bảng dữ liệu(PDF) 10 Page - Texas Instruments |
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LM2743 bảng dữ liệu(HTML) 10 Page - Texas Instruments |
10 / 37 page RFADJ = -5.93 + 3.06 10 7 fSW + 0.24 10 12 (fSW) 2 RFB1 VOUT = RFB1 RFB2 + VFB (VFB = 0.6V) CSS = tSS 60 LM2743 SNVS276F – MAY 2004 – REVISED JANUARY 2012 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The LM2743 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high efficiency buck converters. It has output shutdown (SD), input under-voltage lock-out (UVLO) mode and power good (PWGD) flag (based on over-voltage and under-voltage detection). The over-voltage and under-voltage signals are logically OR'ed to drive the power good signal and provide a logic signal to the system if the output voltage goes out of regulation. Current limit is achieved by sensing the voltage VDS across the low side MOSFET. START UP/SOFT-START When VCC exceeds 2.76V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start capacitor CSS is connected internally to the non-inverting input of the error amplifier. The soft-start period lasts until the voltage on the soft-start capacitor exceeds the LM2743 reference voltage of 0.6V. At this point the reference voltage takes over at the non-inverting error amplifier input. The capacitance of CSS determines the length of the soft-start period, and can be approximated by: (1) Where CSS is in µF and tSS is in ms. During soft start the Power Good flag is forced low and it is released when the FB pin voltage reaches 70% of 0.6V. At this point the chip enters normal operation mode, and the output overvoltage and undervoltage monitoring starts. NORMAL OPERATION While in normal operation mode, the LM2743 regulates the output voltage by controlling the duty cycle of the high side and low side MOSFETs (see Typical Application Circuit). The equation governing output voltage is: (2) The PWM frequency is adjustable between 50 kHz and 1 MHz and is set by an external resistor, RFADJ, between the FREQ pin and ground. The resistance needed for a desired frequency is approximately: (3) Where fSW is in Hz and RFADJ is in kΩ. TRACKING A VOLTAGE LEVEL The LM2743 can track the output of a master power supply during soft-start by connecting a resistor divider to the SS/TRACK pin. In this way, the output voltage slew rate of the LM2743 will be controlled by the master supply for loads that require precise sequencing. When the tracking function is used no soft-start capacitor should be connected to the SS/TRACK pin. Otherwise, a CSS value of at least 1 nF between the soft-start pin and ground should be used. 10 Submit Documentation Feedback Copyright © 2004–2012, Texas Instruments Incorporated Product Folder Links: LM2743 |
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