LMH0346

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SNLS248J – APRIL 2007 – REVISED APRIL 2013

Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low

level. This output functions as the serial clock output when the SCO_EN input is a logic-high level. The SCO_EN

input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2 enabled).

SCO/SDO2 is muted when the OUTPUT MUTE input is a logic low level. When the Bypass mode is activated

and this output is functioning as a serial clock output (SCO_EN is high), the output will also be muted. If an

unsupported data rate is used while in Auto Bypass mode with this output functioning as a serial clock output, the

output is invalid.

Control Inputs and Indicator Outputs

SERIAL DATA RATE SELECTOR

The Serial Data Rate Selector (RATE [1:0]) permits the user to fix the operating serial data rate. The pins have

internal pull-downs which maintain a logic-low input condition unless externally driven to a logic-high condition.

This input also serves to place the device in a test mode. The codes shown in Table 1 select the desired

operating serial data rate. The LMH0346 then enters either the Auto-Rate Detect mode or a single operating rate.

Selecting the 270 Mbps rate mode may also be used when reclocking DVB-ASI data. DVB-ASI data is MPEG2

coded data that is transmitted in 8B10B coding. The device will reclock this data without harmonic locking. Auto-

Rate Detect mode may be used for any supported data rate, including DVB-ASI.

Table 1. Data Rate Select Input Codes

Rate [1:0] Code

Data Rate or Mode

Comments

00

Auto-Rate Detect mode

01

270 Mbps

May be used to support DVB-ASI operation

10

1483/1485 Mbps, 2967/2970 Mbps

LOCK DETECT

The Lock Detect (LD) output, when high, indicates that data is being received and the PLL is locked. LD may be

connected to the OUTPUT MUTE input to mute the data and clock outputs when no data signal is being

received. Note that when the Bypass/Auto Bypass input is set high, Lock Detect will remain low. See Table 2.

OUTPUT MUTE

The OUTPUT MUTE input, when low, mutes the serial data and clock outputs. It may be connected to Lock

Detect or externally driven to mute or un-mute the outputs. If OUTPUT MUTE is connected to LD, then the data

and clock outputs are muted when the PLL is not locked. This function overrides the Bypass function: see

Table 2. OUTPUT MUTE has an internal pull-up device to enable the output by default.

BYPASS/AUTO BYPASS

The Bypass/Auto Bypass input, when high, forces the device to output the data without reclocking it. When this

input is low, the device automatically bypasses the reclocking function when the device is in an unlocked

condition or the detected data rate is a rate which the device does not support. Note that when the Bypass/Auto

Bypass input is set high, Lock Detect will remain low. See Table 2. BYPASS/AUTO BYPASS has an internal pull-

down device.

Table 2. Control Functionality

LOCK DETECT

OUTPUT MUTE

BYPASS/AUTO BYPASS

DEVICE STATUS

0

1

X

PLL unlocked, reclocker bypassed

1

1

0

PLL locked to supported data rate, reclocker not bypassed

X

0

X

Outputs muted

0

LOCK DETECT

X

Outputs muted

1

LOCK DETECT

0

PLL locked to supported data rate, reclocker not bypassed

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