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ADC12DL080 bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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ADC12DL080 bảng dữ liệu(HTML) 1 Page - Texas Instruments |
1 / 35 page ADC12DL080 www.ti.com SNAS345 – FEBRUARY 2006 ADC12DL080 Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling Check for Samples: ADC12DL080 1 FEATURES ADC12DL065, ADC12DL066 23 • Single +3.3V supply operation APPLICATIONS • Internal sample-and-hold • Instrumentation • Internal or External reference • Communications Receivers • Outputs 2.4V to 3.6V compatible • Sonar/Radar • Power down mode • xDSL, Cable Modems • Duty Cycle Stabilizer • Pin compatible with ADC12DL040, DESCRIPTION The ADC12DL080 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 80 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 600 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC12DL080 achieves 11.0 effective bits at Nyquist and consumes just 447mW at 80 MSPS. The Power Down feature reduces power consumption to 50 mW. The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. Duty cycle stabilization and output data format are selectable. The output data can be set for offset binary or two's complement. To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL080 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. Key Specifications VALUE UNIT Resolution 12 Bits Max Conversion Rate 80 MSPS DNL ±0.4 LSB (typ) SNR (fIN=40MHz) 69 dB (typ) SNR (fIN=200MHz) 67 dB (typ) SFDR (fIN=40MHz) 82 dB (typ) SFDR (fIN=200MHz) 81 dB (typ) Power Consumption Operating 447 mW (typ) Power Down 50 mW (typ) Mode 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 TRI-STATE is a registered trademark of National Semiconductor Corporation. 3 All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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