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ADC12DL066 bảng dữ liệu(PDF) 5 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  Dual 12-Bit, 66 Msps, 450 MHz Input Bandwidth A/D Converter w/Internal Reference
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ADC12DL066
www.ti.com
SNAS188F – MAY 2004 – REVISED FEBRUARY 2008
Pin No.
Symbol
Equivalent Circuit
Description
24–29
DA0–DA11
34–39
Digital data output pins that make up the 12-bit conversion results
of their respective converters. DA0 and DB0 are the LSBs, while
DA11 and DB11 are the MSBs of the output words. Output levels
are TTL/CMOS compatible.
42–47
DB0–DB11
52–57
(5)
ANALOG POWER
Positive analog supply pins. These pins should be connected to a
9, 18, 19, 62,
quiet +3.3V source and bypassed to AGND with 0.1 µF capacitors
VA
63
located within 1 cm of these power pins, and with a 10 µF
capacitor.
3, 8, 10, 17,
AGND
The ground return for the analog supply.
20, 61, 64
DIGITAL POWER
Positive digital supply pin. This pin should be connected to the
same quiet +3.3V source as is VA and be bypassed to DGND with
33, 48
VD
a 0.1 µF capacitor located within 1 cm of the power pin and with a
10 µF capacitor.
32, 49
DGND
The ground return for the digital supply.
Positive digital supply pin for the ADC12DL066's output drivers.
This pin should be connected to a voltage source of +2.4V to VD
and be bypassed to DR GND with a 0.1 µF capacitor. If the supply
30, 51
VDR
for this pin is different from the supply used for VA and VD, it should
also be bypassed with a 10 µF capacitor. VDR should never exceed
the voltage on VD. All bypass capacitors should be located within 1
cm of the supply pin.
The ground return for the digital supply for the ADC12DL066's
output drivers. These pins should be connected to the system
23, 31, 40,
DR GND
digital ground, but not be connected in close proximity to the
50, 58
ADC12DL066's DGND or AGND pins. See LAYOUT AND
GROUNDING (Layout and Grounding) for more details.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2004–2008, Texas Instruments Incorporated
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