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ADC12DL066 bảng dữ liệu(PDF) 10 Page - Texas Instruments |
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ADC12DL066 bảng dữ liệu(HTML) 10 Page - Texas Instruments |
10 / 31 page ADC12DL066 SNAS188F – MAY 2004 – REVISED FEBRUARY 2008 www.ti.com AC Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, INT/EXT REF pin = +3.3V, VREF = +1.0V, fCLK = 66 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1) (2) (3) (4) Typical Limits Units Symbol Parameter Conditions (5) (5) (Limits) fCLK1 Maximum Clock Frequency 66 MHz (min) fCLK2 Minimum Clock Frequency 15 MHz tCH Clock High Time 6.6 ns (min) tCL Clock Low Time 6.6 ns (min) tCONV Conversion Latency 6 Clock Cycles rising 6.6 9.0 ns (max) VDR = 2.5V falling 6.0 8.5 ns (max) tOD Data Output Delay after Rising CLK Edge rising 6.4 9.0 ns (max) VDR = 3.3V falling 6.5 9.0 ns (max) tAD Aperture Delay 2 ns tAJ Aperture Jitter 1.2 ps rms tHOLD Clock Edge to Data Transition 8 ns tDIS Data outputs into Hi-Z Mode 10 ns tEN Data Outputs Active after Hi-Z Mode 10 ns 0.1 µF on pins 4, 14; series 1.5 Ω & 1 µF tPD Power Down Mode Exit Cycle 500 µs between pins 5, 6 and between pins 12, 13 (1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per (). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions. (2) To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. (3) With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV. (4) Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. (5) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. COMMON MODE VOLTAGE (VCM) is the common d.c. voltage applied to both input terminals of the ADC. CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. 10 Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC12DL066 |
Số phần tương tự - ADC12DL066_14 |
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Mô tả tương tự - ADC12DL066_14 |
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