ADC12DL066

SNAS188F – MAY 2004 – REVISED FEBRUARY 2008

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AC Electrical Characteristics

(1) (2) (3) (4)

Typical

Limits

Units

Symbol

Parameter

Conditions

(5)

(5)

(Limits)

Maximum Clock Frequency

66

MHz (min)

Minimum Clock Frequency

15

MHz

Clock High Time

6.6

ns (min)

Clock Low Time

6.6

ns (min)

Conversion Latency

6

Clock Cycles

rising

6.6

9.0

ns (max)

falling

6.0

8.5

ns (max)

Data Output Delay after Rising CLK Edge

rising

6.4

9.0

ns (max)

falling

6.5

9.0

ns (max)

Aperture Delay

2

ns

Aperture Jitter

1.2

ps rms

Clock Edge to Data Transition

8

ns

Data outputs into Hi-Z Mode

10

ns

Data Outputs Active after Hi-Z Mode

10

ns

0.1 µF on pins 4, 14; series 1.5

Ω & 1 µF

Power Down Mode Exit Cycle

500

µs

between pins 5, 6 and between pins 12, 13

(1)

(2)

(3)

(4)

(5)

Outgoing Quality Level).

Specification Definitions

APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the

total time of one period. The specification here refers to the ADC clock input signal.

CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is

presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay

plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the

conversion by the pipeline delay.

10

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