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ADC12DC080 bảng dữ liệu(PDF) 3 Page - Texas Instruments

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AGND
VA
AGND
VA
VA
VA
VA
VA
AGND
AGND
VA
AGND
ADC12DC080
www.ti.com
SNAS405B – SEPTEMBER 2007 – REVISED NOVEMBER 2008
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
3
VINA+
13
VINB+
Differential analog input pins. The differential full-scale input signal
level is 2VP-P with each input pin signal centered on a common mode
2
VINA-
voltage, VCM.
14
VINB-
5
VRPA
11
VRPB
7
VCMOA
9
VCMOB
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close to
the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor
should be placed between VRP and VRN as close to the pins as
possible, and a 1 µF capacitor should be placed in parallel.
VRP and VRN should not be loaded. VCMO may be loaded to 1mA for
6
VRNA
use as a temperature stable 1.5V reference.
10
VRNB
It is recommended to use VCMO to provide the common mode
voltage, VCM, for the differential analog inputs.
Reference Voltage. This device provides an internally developed
1.2V reference. When using the internal reference, VREF should be
decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series
59
VREF
inductance (ESL) capacitor.
This pin may be driven with an external 1.2V reference voltage.
This pin should not be used to source or sink current when the
internal reference is used.
DIGITAL I/O
This is a four-state pin controlling the input clock mode and output
data format.
OF/DCS = VA, output data format is 2's complement without duty
cycle stabilization applied to the input clock.
OF/DCS = AGND, output data format is offset binary, without duty
19
OF/DCS
cycle stabilization applied to the input clock.
OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle
stabilization applied to the input clock.
OF/DCS = (1/3)*VA, output data is offset binary with duty cycle
stabilization applied to the input clock.
Copyright © 2007–2008, Texas Instruments Incorporated
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