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ADC12C170 bảng dữ liệu(HTML) 1 Page - Texas Instruments

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ADC12C170
www.ti.com
SNAS374D – DECEMBER 2006 – REVISED APRIL 2009
ADC12C170 12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with CMOS Outputs
Check for Samples: ADC12C170
1
FEATURES
DESCRIPTION
The ADC12C170 is a high-performance CMOS
2
1.1 GHz Full Power Bandwidth
analog-to-digital
converter
capable
of
converting
Internal Sample-and-Hold Circuit
analog input signals into 12-Bit digital words at rates
Low Power Consumption
up to 170 Mega Samples Per Second (MSPS). This
converter uses a differential, pipelined architecture
Internal Precision 1.0V Reference
with digital error correction and an on-chip sample-
Single-Ended or Differential Clock Modes
and-hold circuit to minimize power consumption and
Clock Duty Cycle Stabilizer
the
external
component
count,
while
providing
excellent dynamic performance. A unique sample-
Dual +3.3V and +1.8V Supply Operation
and-hold stage yields a full-power bandwidth of 1.1
Power-Down and Sleep Modes
GHz. The ADC12C170 operates from dual +3.3V and
Offset Binary or 2's Complement Output Data
+1.8V power supplies and consumes 715 mW of
Format
power at 170 MSPS.
Pin-Compatible: ADC14155, ADC11C125,
The separate +1.8V supply for the digital output
ADC11C170
interface allows lower power operation with reduced
48-Pin WQFN Package, (7x7x0.8mm, 0.5mm
noise. A power-down feature reduces the power
consumption to 5 mW while still allowing fast wake-up
Pin-Pitch)
time to full operation. In addition there is a sleep
feature which consumes 50 mW of power and has a
APPLICATIONS
faster wake-up time.
High IF Sampling Receivers
The differential inputs provide a full scale differential
Wireless Base Station Receivers
input swing equal to 2 times the reference voltage. A
Power Amplifier Linearization
stable 1.0V internal voltage reference is provided, or
the ADC12C170 can be operated with an external
Multi-Carrier, Multi-Mode Receivers
reference.
Test and Measurement Equipment
Clock mode (differential versus single-ended) and
Communications Instrumentation
output
data
format
(offset
binary
versus
2's
Radar Systems
complement)
are
pin-selectable.
A
duty
cycle
stabilizer maintains performance over a wide range of
KEY SPECIFICATIONS
input clock duty cycles.
Resolution 12 Bits
The
ADC12C170
is
pin
compatible
with
the
Conversion Rate 170 MSPS
ADC14155, ADC11C125 and ADC11C170.
SNR (fIN = 70 MHz) 67.2 dBFS (typ)
It is available in a 48-lead WQFN package and
SFDR (fIN = 70 MHz) 85.4 dBFS (typ)
operates over the industrial temperature range of
−40°C to +85°C.
ENOB (fIN = 70 MHz) 10.8 bits (typ)
Full Power Bandwidth 1.1 GHz (typ)
Power Consumption 715 mW (typ)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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