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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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LM49370 bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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LM49370 bảng dữ liệu(HTML) 7 Page - Texas Instruments |
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7 / 90 page  LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Electrical Characteristics (1)(2) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C. LM49370 Symbol Parameter Conditions Units Limit(4) Typical(3) (5) Chip Mode '10', fMCLK = 12MHz, fS = 48kHz, 7.9 mA DAC on; PLL off Digital Playback Mode Digital Active Current Chip Mode '10', fMCLK = 13MHz, fPLLOUT = 12MHz, fS = 48kHz; 12.5 14.5 mA(max) DAC + PLL on Chip Mode '10', HP On, SE mode, 9.0 13.5 mA(max) DAC inputs selected Digital Playback Mode Analog Chip Mode '10', HP On, OCL mode, 9.4 13.5 mA(max) Active Current DAC inputs selected Chip Mode '10', LS On, 11.5 15.5 mA(max) DAC inputs selected Analog Playback Mode Digital Active Chip Mode '10', fMCLK = 13MHz, 0.9 1.8 mA(max) Current DAC +ADC + PLL off Chip Mode '10', HP On, SE mode, 5.9 9.5 mA(max) AUX inputs selected Analog Playback Mode Analog Active Chip Mode '10', HP On, OCL mode, 6.3 9.7 mA(max) Current AUX inputs selected Chip Mode '10', LS On, 8.4 12 mA(max) AUX inputs selected Chip Mode '10', fMCLK = 13MHz, fS = CODEC Mode Digital Active Current 2.7 3.5 mA(max) 8kHz, DAC +ADC on; PLL Off CODEC Mode Analog Active Current Chip Mode '10', EP On, 11.2 15.5 mA(max) DAC inputs selected Voice Module Mode Digital Active Chip Mode '10', fMCLK = 13MHz, 0.9 1.8 mA(max) Current DAC +ADC + PLL off Voice Module Mode Analog Active Chip Mode '10', EP + CPOUT on, 7.4 11 mA(max) Current CPIN input selected LOUDSPEAKER AMPLIFIER 8 Ω load, LS_VDD = 5V 1.2 W PLS Max Loudspeaker Power 8 Ω load, LS_VDD = 4.2V 0.9 W 8 Ω load, LS_VDD = 3.3V 0.5 0.43 W (min) 8 Ω load, LS_VDD = 3.3V, LSTHD+N Loudspeaker Harmonic Distortion 0.04 % PO = 400mW 0 dB Input LSEFF Efficiency 84 % MCLK = 12.000 MHz AUX inputs terminated Power Supply Rejection Ration CBYPASS = 1.0 µF PSRRLS 70 dB (Loudspeaker) VRIPPLE = 200 mVP-P fRIPPLE = 217 Hz SNRLS Signal to Noise Ratio From 0 dB Analog AUX input, A-weighted 90 80 dB(min) eN Output Noise(7) A-weighted 62 µV VOS Loudspeaker Offset Voltage 12 mV (7) Disabling or bypassing the PLL will usually result in an improvement in noise measurements. Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM49370 |
Số phần tương tự - LM49370_14 |
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Mô tả tương tự - LM49370_14 |
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