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LMH6514SQENOPB bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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LMH6514SQENOPB bảng dữ liệu(HTML) 7 Page - Texas Instruments |
7 / 29 page LMH6514 www.ti.com SNOSB06 – JANUARY 2008 PIN DESCRIPTIONS Pin Number Symbol Description Analog I/O 6 IN+ Non-inverting analog input. Internally biased to 1.4V. Input voltage should not exceed VCC or go below GND by more than 0.5V. 7 IN − Inverting analog input. Internally biased to 1.4V. Input voltage should not exceed VCC or go below GND by more than 0.5V. If using amplifier single ended this input should be capacitively coupled to ground. 15 OUT − Open collector inverting output. This pin is an output that also requires a power source. This pin should be connected to 5V through either an RF choke or an appropriately sized inductor that can form part of a filter. See Application Information for details. 14 OUT+ Open collector non-inverting output. This pin is an output that also requires a power source. This pin should be connected to 5V through either an RF choke or an appropriately sized inductor that can form part of a filter. See Application Information for details. 16 LOAD − Internal 200 Ω resistor connection to pin 15. This pin can be left floating for higher gain or shorted to pin 13 for lower gain and lower effective output impedance. See Application Information for details. 13 LOAD+ Internal 200 Ω resistor connection to pin 14. This pin can be left floating for higher gain or shorted to pin 16 for lower gain and lower effective output impedance. See Application Information for details. Power 3 VCC 5V power supply pin. Use ceramic, low ESR bypass capacitors. This pin powers everything except the output stage. 5,8 GND Ground pins. Connect to low impedance ground plane. All pin voltages are specified with respect to the voltage on these pins. The exposed thermal pad is also a ground connection. Digital Inputs 11,10,9 GAIN_0 to Gain setting pins. See above table for gain step sizes for each pin. These pins are 3.3V CMOS GAIN_2 logic compatible. 5V inputs may cause damage. 2 LATCH This pin controls the function of the gain setting pins mentioned above. With LATCH in the logic HIGH state the gain is fixed and will not change. With the LATCH in the logic LOW state the gain is set by the state of the gain control pins. Any changes in gain made with the LATCH pin in the LOW state will take effect immediately. This pin is 3.3V CMOS logic compatible. 5V inputs may cause damage. 1,4,12 NC These pins are not connected. They can be grounded or left floating. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMH6514 |
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