©2003 Fairchild Semiconductor Corporation

www.fairchildsemi.com

HCPL0XXX Rev. 1.0.4

8

Package Dimensions

8-pin SOIC Surface Mount

Recommended Pad Layout

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

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Lead Coplanarity: 0.004 (0.10) MAX

0.202 (5.13)

0.182 (4.63)

0.021 (0.53)

0.011 (0.28)

0.050 (1.27) Typ.

0.164 (4.16)

1

8

0.144 (3.66)

0.244 (6.19)

0.224 (5.69)

0.143 (3.63)

0.123 (3.13)

0.008 (0.20)

0.003 (0.08)

0.010 (0.25)

0.006 (0.16)

0.024 (0.61)

0.050 (1.27)

Dimensions in inches (mm).

0.155 (3.94)

0.275 (6.99)

0.060 (1.52)