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STM6519APARUC6F bảng dữ liệu(PDF) 5 Page - STMicroelectronics

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STM6519
Description
Doc ID 022111 Rev 6
5/25
1
Description
The Smart ResetTM devices provide a useful feature which ensures that inadvertent short
reset push-button closures do not cause system resets. This is done by implementing an
extended Smart Reset input delay time (tSRC), which ensures a safe reset and eliminates
the need for a specific dedicated reset button.
This reset configuration provides versatility and allows the application to distinguish between
a software generated interrupt and a hard system reset. When the input push-button is
connected to the microcontroller interrupt input, and is closed for a short time, the processor
can only be interrupted. If the system still does not respond properly, continuing to keep the
push-buttons closed for the extended setup time tSRC causes a hard reset of the processor
through the reset output.
The STM6519 has one Smart Reset input (SR) with preset delayed Smart Reset setup time
(tSRC). The reset output (RST) is asserted after the Smart Reset input is held active for the
selected tSRC delay time. The RST output remains asserted either until the SR input goes to
inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset
pulse duration is fixed for tREC (i.e. factory-programmed). The device fully operates over
a broad VCC range from 2.0 V to 5.5 V.
1.1
Test mode
After pulling SR up to VTEST (VCC + 1.4 V) or above, the counter starts to count the initial
shortened tSRC-INI (42 ms, typ.). After tSRC-INI expires, the RST output either goes down for
tREC (if tREC option is used) or stays low as long as overvoltage on SR is detected (if tREC
option is not used). This is feedback, and the user only knows that the device is locked in
test mode. Each time the SR input is connected to ground in test mode, a shortened
tSRC-SHORT (tSRC/128) is used instead of regular tSRC (0.5 s - 10 s). In this way the device
can be quickly tested without repeating test mode triggering. Return to normal mode is
possible by performing a new startup of the device (i.e. VCC goes to 0 V and back to its
original state).
The advantages of this solution are its high glitch immunity, user feedback regarding entry
into test mode, and testability within the full VCC range.


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