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M-8888 bảng dữ liệu(PDF) 2 Page - Clare, Inc. |
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M-8888 bảng dữ liệu(HTML) 2 Page - Clare, Inc. |
2 / 14 page www.clare.com 2 M-8888 Rev. 1 ing the amplifier inputs at V DD/2. Provisions are made for the connection of a feedback resistor to the op-amp output (GS) for gain adjustment. In a single-ended configuration, the input pins should be connected as shown in the Single-Ended Input Configuration above. Differential Input Configuration above shows the nec- essary connections for a differential input configura- tion. Receiver Section The low and high group tones are separated by apply- ing the DTMF signal to the inputs of two sixth-order Single-Ended Input Configuration Differential Input Configuration Functional Description M-8888 functions consist of a high-performance DTMF receiver with an internal gain setting amplifier and a DTMF generator that contains a tone burst counter for generating precise tone bursts and paus- es. The call progress mode, when selected, allows the detection of call progress tones. A standard 8051, 8086/8 series microprocessor interface allows access to an internal status register, two control registers, and two data registers. Input Configuration The input arrangement consists of a differential input operational amplifier and bias sources (V REF) for bias- Pin Functions Name Description IN+ Noninverting op-amp input. IN- Inverting op-amp input. GS Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor. V REF Reference voltage output. Nominally V DD/2 is used to bias inputs at mid-rail. V SS Negative power supply input. OSC1 DTMF clock/oscillator input. OSC2 Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. TONE Dual tone multifrequency (DTMF) output. WR Write input. A low on this pin when CS is low enables data transfer from the microprocessor. TTL compatible. CS Chip select. TTL input (CS = 0 to select the chip). RS0 Register select input. See Internal Register Functions on page 7. TTL compatible. RD Read input. A low on this pin when CS is low enables data transfer to the microprocessor. TTL compatible.. IRQ /CP Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Timing Diagrams on page 11. D0-D3 Microprocessor data bus. TTL compatible. ESt Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. St/GT Steering input/guard time output (bidirectional). A voltage greater than V TSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than V TSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. V DD Positive power supply input. |
Số phần tương tự - M-8888 |
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Mô tả tương tự - M-8888 |
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