công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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LM7372MR bảng dữ liệu(PDF) 2 Page - National Semiconductor (TI) |
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LM7372MR bảng dữ liệu(HTML) 2 Page - National Semiconductor (TI) |
2 / 26 page OUT B 1 2 3 4 5 6 7 8 OUT A -IN A +IN A V - V + -IN B +IN B - + + - A B OUT A OUT B 1 2 8 -IN +IN V- V+ -IN +IN + - + - A B 7 6 5 4 3 16 15 14 13 12 11 10 9 NC NC NC NC * * * * LM7372 SNOS926E – MAY 1999 – REVISED MARCH 2013 www.ti.com Connection Diagrams * Heatsink Pins.(1) Figure 2. 16-Pin SOIC, Top View Figure 3. 8-Pin SO PowerPAD, Top View NOTE For SO PowerPAD package the exposed pad should be tied either to V− or left electrically floating. (Die attach material is conductive and is internally tied to V−) (1) The maximum power dissipation is a function of T(JMAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (T(JMAX) – TA)/θJA. All numbers apply for packages soldered directly into a PC board. The value for θJA is 106°C/W for the 16-Pin SOIC package. With a total area of 4sq. in of 1oz CU connected to pins 1,6,8,9 & 16, θJA for the 16-Pin SOIC is decreased to 70°C/W. 8-Pin SO PowerPAD package θJA is with 2 in 2 heatsink (top and bottom layer each) and 1 oz. copper (see Table 2). These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM7372 |
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Mô tả tương tự - LM7372MR |
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