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AD5171BRJ100-R2 bảng dữ liệu(PDF) 4 Page - Analog Devices |
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AD5171BRJ100-R2 bảng dữ liệu(HTML) 4 Page - Analog Devices |
4 / 24 page AD5171 Rev. D | Page 4 of 24 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS8, 13, 14 –3 dB Bandwidth BW_5k RAB = 5 kΩ, code = 0x20 1500 kHz BW_10k RAB = 10 kΩ, code = 0x20 600 kHz BW_50k RAB = 50 kΩ, code = 0x20 110 kHz BW_100k RAB = 100 kΩ, code = 0x20 60 kHz Total Harmonic Distortion THD VA = 1 V rms, RAB = 10 kΩ, VB = 0 V dc, f = 1 kHz 0.05 % Adjustment Settling Time tS1 VA = 5 V ± 1 LSB error band, VB = 0 V, measured at VW 5 μs Power-Up Settling Time After Fuses Blown tS2 VA = 5 V ±1 LSB error band, VB = 0 V, measured at VW 5 μs Resistor Noise Voltage eN_WB RAB = 5 kΩ, f = 1 kHz, code = 0x20 8 nV/√Hz RAB = 10 kΩ, f = 1 kHz, code = 0x20 12 nV/√Hz 1 Typical specifications represent average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. 6 Guaranteed by design; not subject to production test. 7 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull- up resistors. 8 Guaranteed by design; not subject to production test. 9 Different from operating power supply; power supply for OTP is used one time only. 10 Different from operating current; supply current for OTP lasts approximately 400 ms for one-time need only. 11 See Figure 24 for the energy plot during the OTP program. 12 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 13 Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 14 All dynamic characteristics use VDD = 5 V. |
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