9

®

ADS8321

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

Analog Input Sample Time

4.5

5.0

Clk Cycles

Conversion Time

16

Clk Cycles

Throughput Rate

100

kHz

CS Falling to

0

ns

DCLOCK LOW

CS Falling to

20

ns

DCLOCK Rising

DCLOCK Falling to

5

15

ns

DCLOCK Falling to Next

30

50

ns

70

100

ns

20

50

ns

Enabled

5

25

ns

7

25

ns

FIGURE 6. ADS8321 Basic Timing Diagrams.

AVERAGING

The noise of the A/D converter can be compensated by

averaging the digital codes. By averaging conversion results,

transition noise will be reduced by a factor of 1/

√n, where n

is the number of averages. For example, averaging 4 conver-

sion results will reduce the transition noise by 1/2 to

±0.25

LSBs. Averaging should only be used for input signals with

frequencies near DC.

For AC signals, a digital filter can be used to low pass filter

and decimate the output codes. This works in a similar

manner to averaging; for every decimation by 2, the signal-

to-noise ratio will improve 3dB.

DIGITAL INTERFACE

SIGNAL LEVELS

The digital inputs of the ADS8321 can accommodate logic

input, then that IC may require more supply current than

normal and may have a slightly longer propagation delay.

SERIAL INTERFACE

The ADS8321 communicates with microprocessors and other

digital systems via a synchronous 3-wire serial interface as

shown in Figure 6 and Table I. The DCLOCK signal syn-

chronizes the data transfer with each bit being transmitted on

the falling edge of DCLOCK. Most receiving systems will

capture the bitstream on the rising edge of DCLOCK. How-

system can use the falling edge of DCLOCK to capture each

bit.

A falling CS signal initiates the conversion and data transfer.

The first 4.5 to 5.0 clock periods of the conversion cycle are

used to sample the input signal. After the fifth falling

value for one clock period. For the next 16 DCLOCK

cant bit first. After the least significant bit (B0) has been

output, subsequent clocks will repeat the output data but in

a least significant bit first format.

will tri-state. Subsequent clocks will have no effect on the

converter. A new conversion is initiated only when CS has

been taken HIGH and returned LOW.

CS/SHDN

D

OUT

DCLOCK

Complete Cycle

Power Down

Conversion

Sample

Use positive clock edge for data transfer

t

SUCS

t

CONV

t

SMPL

NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles.

If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.

B15

(MSB)

B14 B13 B12 B11 B10 B9

B8

B0

(LSB)

B7

B1

B6

B2

B5

B3

B4

Hi-Z

0

Hi-Z

t

CSD