7

®

ADS7834

1

2

3

4

8

7

6

5

+V

CC

CLK

DATA

CONV

V

REF

+IN

–IN

GND

ADS7834

0.1µF

+5V

0.1µF

10µF

Serial Clock

from

Microcontroller

or DSP

Serial Data

Convert Start

+

2.2µF

+

0V to 2.5V

Analog Input

FIGURE 1. Basic Operation of the ADS7834.

THEORY OF OPERATION

The ADS7834 is a high speed successive approximation

register (SAR) analog-to-digital converter (A/D) with an

internal 2.5V bandgap reference. The architecture is based

on capacitive redistribution which inherently includes a

sample/hold function. The converter is fabricated on a 0.6

µ

CMOS process. See Figure 1 for the basic operating circuit

for the ADS7834.

The ADS7834 requires an external clock to run the conver-

sion process. This clock can vary between 200kHz (12.5kHz

throughput) and 8MHz (500kHz throughput). The duty cycle

of the clock is unimportant as long as the minimum HIGH

and LOW times are at least 50ns and the clock period is at

least 125ns. The minimum clock frequency is set by the

leakage on the capacitors internal to the ADS7834.

The analog input is provided to two input pins: +IN and –IN.

When a conversion is initiated, the differential input on these

pins is sampled on the internal capacitor array. While a

conversion is in progress, both inputs are disconnected from

any internal function.

The range of the analog input is set by the voltage on the

is 0V to 2.5V. An external reference voltage can be placed

external voltage is 2.0V to 2.55V, giving an input voltage

range of 2.0V to 2.55V.

The digital result of the conversion is provided in a serial

manner, synchronous to the CLK input. The result is pro-

vided most significant bit first and represents the result of

the conversion currently in progress—there is no pipeline

delay. By properly controlling the CONV and CLK inputs,

it is possible to obtain the digital result least significant bit

first.

ANALOG INPUT

The +IN and –IN input pins allow for a differential input

signal to be captured on the internal hold capacitor when the

converter enters the hold mode. The voltage range on the

–IN input is limited to –0.2V to 0.2V. Because of this, the

differential input can be used to reject only small signals that

are common to both inputs. Thus, the –IN input is best used

to sense a remote ground point near the source of the +IN

signal. If the source driving the +IN signal is nearby, the

–IN should be connected directly to ground.

The input current into the analog input depends on input

voltage and sample rate. Essentially, the current into the

device must charge the internal hold capacitor (typically

20pF) during the sample period. After this capacitance has

been fully charged, there is no further input current. The

source of the analog input voltage must be able to charge the

input capacitance to a 12-bit settling level within the sample

period—which can be as little as 350ns in some operating

modes. While the converter is in the hold mode or after the

sampling capacitor has been fully charged, the input imped-

ance of the analog input is greater than 1G

Ω.

Care must be taken regarding the input voltage on the +IN

and –IN pins. To maintain the linearity of the converter, the

+IN input should remain within the range of GND – 200mV

GND – 200mV or exceed GND + 200mV. Outside of these

ranges, the converter’s linearity may not meet specifications.

REFERENCE

scale range of the analog input. The ADS7834 can operate

with a reference in the range of 2.0V to 2.55V, for a full-

scale range of 2.0V to 2.55V.

buffer drives the capacitor DAC portion of the converter.

This is important because the buffer greatly reduces the

dynamic load placed on the reference source. However, the

from the SAR conversion process. These can be reduced by

sections that follow.

INTERNAL REFERENCE

The ADS7834 contains an on-board 2.5V reference, result-

ing in a 0V to 2.5V input range on the analog input. The

specification table gives the various specifications for the