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ADS7832BN bảng dữ liệu(PDF) 10 Page - Burr-Brown (TI) |
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ADS7832BN bảng dữ liệu(HTML) 10 Page - Burr-Brown (TI) |
10 / 15 page ADS7832 10 ® PIN FUNCTION DESCRIPTION D0 Mode Status If LOW, Transparent Mode enabled for data latches. If HIGH, latched Output Mode enabled. D1 CAL Flag If HIGH, calibration cycle in progress. D2 Pin 26 Status If LOW, pin 26 used as input to initiate calibration cycle. If HIGH, pin 26 used as input to control sample-to-hold timing. D3 Power Down Status If HIGH, in Power Down Mode (Power Down Mode is the default condition). D4 Reserved for factory use. D5 POWER FAIL Flag If HIGH, a power supply failure has occurred (supply fell below 2.7V). Always write as LOW. D6 CAL ERROR Flag If HIGH, an overflow occurred during calibration. D7 BUSY Flag If HIGH, conversion or calibration in progress. NOTE: These data are transferred to the bus when a read cycle is initiated with SFR and HBE HIGH. Reading the SFR with SFR HIGH and HBE LOW is reserved for factory use at this time, and will yield unpredictable data. critical parameters are guaranteed over the full –40 °C to +85 °C operating range for ease of system design. SPECIAL FUNCTION REGISTER (SFR) An internal register is available, either to determine addi- tional data concerning the ADS7832, or to write additional instructions to the converter. Table II shows the data in the Special Function Register that will be transferred to the output bus by driving HBE HIGH (with SFR HIGH) and initiating a read cycle (driving RD and CS LOW with WR HIGH.) The Power Fail flag in the SFR is set when the power supply falls below about 2.7V. The flag also means that a new calibration has been started, ADS7832 provides two modes for reading the conversion results. At power-up, the converter is set in the Transparent Mode. TRANSPARENT MODE This is the default mode for ADS7832. In this mode, the conversion decisions from the successive approximation register are latched into the output register as they are made. Thus, the High byte (the 4 MSBs) can be read after the end of the ninth clock cycle (five clock cycles for the mux settling, sample acquisition and auto-zeroing of the com- parator, followed by the four clock cycles for the 4MSB decisions.) The complete 12-bit data is available after BUSY has gone HIGH, or the internal status flag goes LOW (D7 when HBE is HIGH). LATCHED OUTPUT MODE This mode is activated by writing a HIGH to D0 in the Special Function Register with CS and WR LOW and SFR and HBE HIGH. (See the discussion of the Special Function Register below.) In this mode, the data from a conversion is latched into the output buffers only after a conversion is complete, and remains there until the next conversion is completed. The conversion result is valid during the next conversion. This allows the data to be read even after a new conversion is started, for faster system throughput. TIMING CONSIDERATIONS Table I and Figures 3 through 9 show the digital timing of ADS7832 under the various operating modes. All of the TABLE II. Reading the Special Function Register. SYMBOL PARAMETER(1) MIN TYP MAX UNITS t1 CS to WR Setup Time(2) 00 0 ns t2 WR or CAL Pulse Width 100 ns t3 CS to WR Hold Time(2) 00 0 ns t4 WR to BUSY Propagation Delay 20 50 150 ns t5 A0, A1, HBE, SFR Valid to WR Setup Time 0 ns t6 A0, A1, HBE, SFR Valid to WR Hold Time 20 ns t7 BUSY to CS Setup Time 0 ns t8 CS to RD Setup Time(2) 00 0 ns t9 RD Pulse Width 100 ns t10 CS to RD Hold Time(2) 00 0 ns t11 HBE, SFR to RD Setup Time 50 ns t12 HBE, SFR to RD Hold Time 0 ns t13 RD to Valid Data (Bus Access Time)(3) 80 150 ns t14 RD to Hi-Z Delay (Bus Release Time)(3) 90 180 ns t15 RD to Hi-Z Delay For SFR(3) 20 60 ns t16 Data Valid to WR Setup Time 100 ns t17 Data Valid to WR Hold Time 20 ns t18 Acquisition Time. Pin 26 LOW with D2 in SFR HIGH 2.5 µs t19 Sample-to-Hold Aperture Delay. (D2 in SFR HIGH) 5 ns t20 Delay from rising edge on pin 26 to start of conversion. 1.5 CLK cycles (D2 in SFR HIGH) NOTES: (1) All input control signals are specified with tRISE = tFALL = 20ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Data is timed from VIH, VIL, VOH or VOL. (2) The internal RD pulse is performed by a NOR wiring of CS and RD. The internal WR pulse is performed by a NOR wiring of CS and WR. (3) Figures 8 and 9 show the measurement circuits and pulse diagrams for testing transitions to and from Hi-Z states. TABLE I. Timing Specifications (CLK = 2MHz external, T A = –40°C to +85°C). |
Số phần tương tự - ADS7832BN |
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Mô tả tương tự - ADS7832BN |
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