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ADS7832BP bảng dữ liệu(PDF) 4 Page - Burr-Brown (TI) |
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ADS7832BP bảng dữ liệu(HTML) 4 Page - Burr-Brown (TI) |
4 / 15 page ADS7832 4 ® SPECIFICATIONS ADS7832 Electrical Specifications with 5V Supply VA = VD = 5V ±10%; VREF+ = 5.0V; VREF– = AGND = DGND = 0V; CLK = 1MHz external 50% ±2% Duty Cycle, TA = –40°C to +85°C, after calibration at any temperature, unless otherwise specified. ADS7832BP/ADS7832BN PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 12 Bits ANALOG INPUT Voltage Input Range VD = VA = VREF+ = 5V 0 5 V Input Capacitance 40 pF On State Bias Current 100 nA Off State Bias Current TA = +25°C10 nA TA = –40°C to +85°C 100 nA On Resistance Multiplexer 400 Ω Off Resistance Multiplexer 10 M Ω Channel Separation FIN = 1kHz, VD = VA = VREF+ = 5V 0.5 LSB REFERENCE INPUT For Specified Performance: VREF = VA = 5V VREF+ VA V VREF– 0V For Derated Performance(2):(VREF+) – (VREF–) ≥ 2.5V VREF+ 2.5 VA V VREF– 01 V Input Reference Current 100 200 µA THROUGHPUT SPEED Conversion Time With External Clock (Including CLK = 2MHz 8.5 µs Multiplexer Settling Time and Acquisition Time) CLK = 1MHz 17 µs CLK = 500kHz 34 µs With Internal Clock Using Recommended TA = +25°C30 µs Clock Components TA = –40°C to +85°C30 µs Slew Rate 2 mV/ µs Multiplexer Settling Time to 1/2 LSB 0.5 µs Multiplexer Access Time 20 ns SAMPLING DYNAMICS Full Power Bandwidth –3dB 4 MHz Aperture Jitter 10 ps Aperture Delay SRF D2 LOW(3) 2.5 µs SFR D2 HIGH 5 ns DC ACCURACY Integral Nonlinearity, All Channels SFR D2 LOW ±0.75 LSB(4) SFR D2 HIGH, Internal Clock or Sampling ±0.5 LSB Command Synchronous to External Clock SFR D2 HIGH, Sampling ±0.6 LSB Command Asynchronous to External Clock Differential Nonlinearity ±0.75 LSB No Missing Codes Guaranteed Gain Error All Channels ±0.50 LSB Gain Error Drift Between Calibration Cycles ±0.2 ppm/ °C Offset Error All Channels SFR D2 LOW ±0.75 LSB SFR D2 HIGH, Internal Clock or Sampling ±1 LSB Command Synchronous to External Clock SFR D2 HIGH, Sampling ±4 LSB Command Asynchronous to External Clock Offset Error Drift Between Calibration Cycles SFR D2 LOW ±0.2 ppm/ °C SFR D2 HIGH, Internal Clock or Sampling ±0.5 ppm/ °C Command Synchronous to External Clock SFR D2 HIGH, Sampling ±1 ppm/ °C Command Asynchronous to External Clock Channel-to-Channel Mismatch SFR D2 LOW ±0.25 LSB SFR D2 HIGH, Internal Clock or Sampling ±0.5 LSB Command Synchronous to External Clock SFR D2 HIGH, Sampling ±1.0 LSB Command Asynchronous to External Clock Power Supply Sensitivity VD = VA = +5V ±10% (without recalibration) ±0.125 LSB |
Số phần tương tự - ADS7832BP |
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Mô tả tương tự - ADS7832BP |
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