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ADS7824U bảng dữ liệu(PDF) 7 Page - Burr-Brown (TI) |
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ADS7824U bảng dữ liệu(HTML) 7 Page - Burr-Brown (TI) |
7 / 16 page 7 ® ADS7824 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ADS7824 Parallel Output ±10V +5V +5V(1) 0.1µF 10µF + + D6 D5 D4 LOW LOW LOW D9 D8 D11 Pin 21 LOW D10 D7 D1 D0 D3 Pin 21 HIGH NOTE: (1) PAR/SER = 5V D2 LOW 2.2µF + 2.2µF + Convert Pulse BUSY R/C BYTE 40ns min 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ADS7824 Serial Output ±10V +5V 0.1µF 10µF + + NOTES: (1) DATACLK (pin 15) is an output when EXT/INT (pin 12) is LOW and an input when EXT/INT is HIGH. (2) NC = no connection. (3) PAR/SER = 0V. 2.2µF + 2.2µF + Convert Pulse BUSY SDATA DATACLK(1) EXT/INT SYNC R/C 40ns min NC(2) NC(2) NC(2) (3) BASIC OPERATION PARALLEL OUTPUT Figure 1a shows a basic circuit to operate the ADS7824 with parallel output (Channel 0 selected). Taking R/C (pin 22) LOW for 40ns (12 µs max) will initiate a conversion. BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, the 8 most significant bits will be valid when pin 24 rises; if BYTE is HIGH, the 4 least significant bits will be valid when BUSY rises. Data will be output in Binary Two’s Complement format. BUSY going HIGH can be used to latch the data. After the first byte has been read, BYTE can be toggled allowing the remaining byte to be read. All convert commands will be ignored while BUSY is LOW. The ADS7824 will begin tracking the input signal at the end of the conversion. Allowing 25 µs between convert com- mands assures accurate acquisition of a new signal. SERIAL OUTPUT Figure 1b shows a basic circuit to operate the ADS7824 with serial output (Channel 0 selected). Taking R/C (pin 22) LOW for 40ns (12 µs max) will initiate a conversion and output valid data from the previous conversion on SDATA (pin 16) synchronized to 12 clock pulses output on DATACLK (pin 15). BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the serial data has been transmitted. Data will be output in Binary Two’s Complement format, MSB first, and will be valid on both the rising and falling edges of the data clock. BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW. The ADS7824 will begin tracking the input signal at the end of the conversion. Allowing 25 µs between convert com- mands assures accurate acquisition of a new signal. FIGURE 1. Basic Connection Diagram, (a) Parallel Output, (b) Serial Output. |
Số phần tương tự - ADS7824U |
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Mô tả tương tự - ADS7824U |
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