4

®

ADS7824

1

AGND1

Analog Ground. Used internally as ground reference point.

2

Analog Input Channel 0. Full-scale input range is

±10V.

3

Analog Input Channel 1. Full-scale input range is

±10V.

4

Analog Input Channel 2. Full-scale input range is

±10V.

5

Analog Input Channel 3. Full-scale input range is

±10V.

6

CAP

Internal Reference Output Buffer. 2.2

µF Tantalum to ground.

7

REF

Reference Input/Output. Outputs +2.5V nominal. If used externally, must be buffered to maintain ADS7825 accuracy.

Can also be driven by external system reference. In both cases, bypass to ground with a 2.2

µF Tantalum capacitor.

8

AGND2

Analog Ground.

9

D7

O

Parallel Data Bit 7 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.

10

D6

O

Parallel Data Bit 6 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.

11

D5

O

Parallel Data Bit 5 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.

12

D4

I/O

Parallel Data Bit 4 if PAR/SER HIGH; if PAR/SER LOW, a LOW level input here will transmit serial data on SDATA from

the previous conversion using the internal serial clock; a HIGH input here will transmit serial data using an external serial

clock input on DATACLK (D2). See Table I.

13

D3

O

Parallel Data Bit 3 if PAR/SER HIGH; SYNC output if PAR/SER LOW. See Table I.

14

DGND

Digital Ground.

15

D2

I/O

Parallel Data Bit 2 if PAR/SER HIGH; if PAR/SER LOW, this will output the internal serial clock if EXT/INT (D4) is LOW;

will be an input for an external serial clock if EXT/INT (D4) is HIGH. See Table I.

16

D1

O

Parallel Data Bit 1 if PAR/SER HIGH; SDATA serial data output if PAR/SER LOW. See Table I.

17

D0

I/O

Parallel Data Bit 0 if PAR/SER HIGH; TAG data input if PAR/SER LOW. See Table I.

18

A1

I/O

Channel Address. Input if CONTC LOW, output if CONTC HIGH. See Table I.

19

A0

I/O

Channel Address. Input if CONTC LOW, output if CONTC HIGH. See Table I.

20

PAR/SER

I

Select Parallel or Serial Output. If HIGH, parallel data will be output on D0 thru D7. If LOW, serial data will be output on

SDATA. See Table I and Figure 1.

21

BYTE

I

Byte Select. Only used with parallel data, when PAR/SER HIGH. Determines which byte is available on D0 thru D7.

Changing BYTE with CS LOW and R/C HIGH will cause the data bus to change accordingly. LOW selects the 8 MSBs;

HIGH selects the 4 LSBs, see Figures 2 and 3.

22

R/C

I

Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a

conversion. With CS LOW, a rising edge on R/C enables the output data bits if PAR/SER HIGH, or starts transmission

of serial data if PAR/SER LOW and EXT/INT HIGH.

23

CS

I

Chip Select. Internally OR'd with R/C. With CONTC LOW and R/C LOW, a falling edge on CS will initiate a conversion.

With R/C HIGH, a falling edge on CS will enable the output data bits if PAR/SER HIGH, or starts transmission of serial

data if PAR/SER LOW and EXT/INT HIGH.

24

BUSY

O

Busy Output. Falls when conversion is started; remains LOW until the conversion is completed and the data is latched

into the output register. In parallel output mode, output data will be valid when BUSY rises, so that the rising edge can

be used to latch the data.

25

CONTC

I

Continuous Conversion Input. If LOW, conversions will occur normally when initiated using CS and R/C; if HIGH,

acquisition and conversions will take place continually, cycling through all four input channels, as long as CS, R/C and

PWRD are LOW. See Table I. For serial mode only.

26

PWRD

I

Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the

previous conversion are maintained in the output register. In the continuous conversion mode, the multiplexer address

channel is reset to channel 0

27

Supply Input. Nominally +5V. Connect directly to pin 28. Decouple to ground with 0.1

µF ceramic and 10µF Tantalum

capacitors.

28

Supply Input. Nominally +5V. Connect directly to pin 27.

PIN #

NAME

I/O

DESCRIPTION

PIN ASSIGNMENTS