công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADS7813 bảng dữ liệu(PDF) 9 Page - Burr-Brown (TI) |
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ADS7813 bảng dữ liệu(HTML) 9 Page - Burr-Brown (TI) |
9 / 17 page 9 ® ADS7813 BINARY TWO’S COMPLEMENT DIGITAL OUTPUT TABLE III. Ideal Input Voltage and Corresponding Digital Output for Two Common Input Ranges. DESCRIPTION ANALOG INPUT Full-Scale Range ±10V 0.5V to 4.5V Least Significant Bit (LSB) 305 µV61µV BINARY CODE HEX CODE +Full Scale –1LSB 9.999695V 4.499939V 0111 1111 1111 1111 7FFF Midscale 0V 2.5V 0000 0000 0000 0000 0000 Midscale –1LSB –305 µV 2.499939 µV 1111 1111 1111 1111 FFFF –Full Scale –10V 0.5V 10000 0000 0000 0000 8000 Q D S0 Q Update of the shift register occurs just prior to BUSY Rising(1) D S1 Q D S2 Q D S14 Q D S15 Q Shift Register Working Register Converter Core D SOUT Q D W0 Q Each flip-flop in the working register is latched as the conversion proceeds D W1 Q D W2 Q D W14 Q D W15 ••• Delay DATA BUSY DATACLK CDAC Control Logic Clock REF EXT/INT CONV CS NOTE: (1) If EXT/INT is HIGH (external clock), DATACLK is HIGH, and CS is LOW during this time, the shift register will not be updated and the conversion result will be lost. FIGURE 3. Block Diagram of the ADS7813’s Digital Inputs and Outputs. READING DATA The ADS7813’s digital output is in Binary Two’s Comple- ment (BTC) format. Table III shows the relationship be- tween the digital output word and the analog input voltage under ideal conditions. Figure 3 shows the relationship between the various digital inputs, digital outputs, and internal logic of the ADS7813. Figure 4 shows when the internal shift register of the ADS7813 is updated and how this relates to a single conver- sion cycle. Together, these two figures point out a very important aspect of the ADS7813: the conversion result is not available until after the conversion is complete. The implications of this are discussed in the following sections. FIGURE 4. Timing of the Shift Register Update. CONV t 6 – t25 t 25 BUSY NOTE: Update of the internal shift register occurs in the shaded region. If EXT/INT is HIGH, then DATACLK must be LOW or CS must be HIGH during this time. |
Số phần tương tự - ADS7813 |
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Mô tả tương tự - ADS7813 |
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