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3 / 14 page 74LVC00A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 — 25 April 2012 3 of 14 NXP Semiconductors 74LVC00A Quad 2-input NAND gate 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care 7. Limiting values [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO14 packages: above 70 °C derate linearly with 8 mW/K. For (T)SSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. 8. Recommended operating conditions Table 3. Function selection[1] Input Output nA nB nY LX H XL H HHL Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +6.5 V IIK input clamping current VI < 0 V −50 - mA VI input voltage [1] −0.5 +6.5 V IOK output clamping current VO > VCC or VO < 0 V - ±50 mA VO output voltage output in HIGH or LOW-state [2] −0.5 VCC + 0.5 V IO output current VO = 0 V to VCC - ±50 mA ICC supply current - 100 mA IGND ground current −100 - mA Ptot total power dissipation Tamb = −40 °C to +125 °C [3] - 500 mW Tstg storage temperature −65 +150 °C Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 1.65 - 3.6 V functional 1.2 - - V VI input voltage 0 - 5.5 V VO output voltage output HIGH or LOW state 0 - VCC V Tamb ambient temperature −40 - +125 °C Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V |
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