®

ADC76

4

“0”

“1”

“1”

“0”

“0”

“1”

“1”

“1”

“0”

“1”

“1”

“0”

“1”

“0”

“0”

“1”

“1”

“0”

“0”

“0”

“1”

“1”

“1”

“1”

“1”

“1”

“0”

“0”

“0”

“1”

“1”

“0”

MSB

1

2

34

5

6

7

8

9

10

11

12

13

14

15

16

Maximum Throughput Time

Conversion Time

(2)

Convert Command

(1)

Internal Clock

Status (EOC)

MBS

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

Bit 16

Serial Data Out

NOTES: (1) The convert command must be at least 50ns wide and must remain low during a conversion. The conversion is

initiated by the “trailing edge” of the convert command. (2) 17

µs for 16 bits.

FIGURE 1. ADC76 Timing Diagram.

40-125ns

Bit 16

Status

Bit 16

Valid

FIGURE 2. Timing Relationship of Serial Data to Clock.

FIGURE 3. Timing Relationship of Valid Data to Status.

BINARY

(BIN) OUTPUT

INPUT VOLTAGE RANGE AND LSB VALUES

Analog Input

Voltage Range

Defined As:

±10V

±5V

±2.5V

0 to +10V

0 to +5V

0 to +20V

Code

Designation

One Least

FSR

20V

10V

5V

10V

5V

20V

Significant

Bit (LSB)

n = 12

4.88mV

2.44mV

1.22mV

2.44mV

1.22mV

4.88mV

n = 13

2.44mV

1.22mV

610

µV

1.22mV

610

µV

2.44mV

n = 14

1.22mV

610

µV

305

µV

610

µV

305

µV

1.22mV

Transition Values

MSB LSB

+Full Scale

+10V–3/2LSB

+5V–3/2LSB

+2.5V–3/2LSB

+10V–3/2LSB

+5V–3/2LSB

+20V–3/2LSB

011 ... 111

Mid Scale

0

0

0

+5V

+2.5V

+10V

111 ... 110

–Full Scale

–10V +1/2LSB

–5V +1/2LSB

–2.5V +1/2LSB

0 +1/2LSB

0 +1/2LSB

0 +1/2LSB

NOTES: (1) COB = Complementary Offset Binary. (2) Complementary Two’s Complement—obtained by inverting the most significant bit MSB (pin 1).

(3) CSB = Complementary Straight Binary. (4) Voltages given are the nominal value for transition to the code specified.

Serial

Out

Clock

Out

40-125ns

40-125ns

TABLE I. Input Voltages, Transition Values, LSB Values, and Code Definitions.