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ADS42LB69IRGCT bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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ADS42LB69IRGCT bảng dữ liệu(HTML) 7 Page - Texas Instruments |
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7 / 80 page  CLKIN SYNCIN t SU_SYNCIN Sample N t H_SYNCIN ADS42LB49 ADS42LB69 www.ti.com SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013 TIMING REQUIREMENTS: General Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 3.3 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.7 V to 1.9 V. PARAMETER DESCRIPTION MIN TYP MAX UNIT tA Aperture delay 0.5 0.7 1.1 ns Aperture delay matching Between two channels of the same device ±70 ps Between two devices at the same temperature and Variation of aperture delay ±150 ps supply voltage. tJ Aperture jitter 85 fS rms Time to valid data after coming out of STANDBY 50 100 µs mode Wakeup time Time to valid data after coming out of GLOBAL power-down mode (in this mode, both channels 250 1000 µs power-down) Clock Default latency after reset 14 cycles Clock ADC latency(1) Normal OVR latency 14 cycles Clock Fast OVR latency 9 cycles Setup time for SYNCIN Referenced to input clock tSU_SYNCIN 400 ps rising edge Hold time for SYNCIN Referenced to input clock tH_SYNCIN 100 ps rising edge (1) Overall latency = ADC latency + tPDI. TIMING DIAGRAM: General Figure 1. Timing Diagram for SYNCINP and SYNCINM Inputs Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADS42LB49 ADS42LB69 |
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