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ADS42LB69IRGCR bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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ADS42LB69IRGCR bảng dữ liệu(HTML) 1 Page - Texas Instruments |
1 / 80 page CLKINP, CLKINM INAP, INAM Configuration Registers Common Mode VCM DACLKP, D M ACLK DAFRAMEP, M AFRAME INBP, M INB 14-, 16-Bit ADC Digital Block Digital Gain and Test Patterns ADS42LB49, ADS42LB69 SYNCINP, M SYNCIN OVRA DA[3:0]P, DA[3:0]M Output Formatter QDR LVDS DBCLKP, M BCLK DBFRAMEP, M BFRAME DB[3:0]P, M B[3:0]M Output Formatter QDR LVDS OVRB Divide by 1,2,4 Delay 14-, 16-Bit ADC Digital Block Digital Gain and Test Patterns -120 -100 -80 -60 -40 -20 0 0 25 50 75 100 125 Frequency (MHz) FFT for 170MHz Input Signal Fs = 250Msps Fin = 170MHz Ain = -1dBFS HD2 = 90dBc HD3 = 89dBc Non HD2,3 = 100dBc ADS42LB49 ADS42LB69 www.ti.com SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters Check for Samples: ADS42LB49, ADS42LB69 1 FEATURES APPLICATIONS 2 • Dual Channel • Communication and Cable Infrastructure • 14- and 16-Bit Resolution • Multi-Carrier, Multimode Cellular Receivers • Maximum Clock Rate: 250 MSPS • Radar and Smart Antenna Arrays • Analog Input Buffer with High Impedance Input • Broadband Wireless • Flexible Input Clock Buffer with • Test and Measurement Systems Divide-by-1, -2, and -4 • Software-Defined and Diversity Radios • 2-VPP and 2.5-VPP Differential Full-Scale Input • Microwave and Dual-Channel I/Q Receivers (SPI-Programmable) • Repeaters • DDR or QDR LVDS Interface • Power Amplifier Linearization • 64-Pin QFN Package (9-mm x 9-mm) • Power Dissipation: 820 mW/ch DESCRIPTION The ADS42LB49 and ADS42LB69 are a family of • Aperture Jitter: 85 fS high-linearity, dual-channel, 14- and 16-bit, • Internal Dither 250-MSPS, analog-to-digital converters (ADCs) • Channel Isolation: 100 dB supporting DDR and QDR LVDS output interfaces. The buffered analog input provides uniform input • Performance at fIN = 170 MHz at 2 VPP, –1 dBFS impedance across a wide frequency range while – SNR: 73.2 dBFS minimizing sample-and-hold glitch energy. A – SFDR: sampling clock divider allows more flexibility for – 87 dBc (HD2 and HD3) system clock architecture design. The ADS42LB49 and ADS42LB69 provide excellent spurious-free – 100 dBc (Non HD2 and HD3) dynamic range (SFDR) over a large input frequency • Performance at fIN = 170 MHz: range with low-power consumption. 2.5 VPP, –1 dBFS – SNR: 74.9 dBFS Table 1. Family Comparison – SFDR: INTERFACE 14-BIT 16-BIT OPTION – 85 dBc (HD2 and HD3) DDR, QDR LVDS ADS42LB49 ADS42LB69 – 97 dBc (Non HD2 and HD3) JESD204B ADS42JB49 ADS42JB69 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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